Abstract ▼ AI-Helper

Recently High-Definition TV camera and broadcasting system were developed in U.S.A and Japan. Korea is developing HDTV system. HDTV system manipulates and communicates digital data between camera & broadcasting system in contrast to NTSC TV system. These Data are composed of 20 bits, 74.25 Mwords/s....

Recently High-Definition TV camera and broadcasting system were developed in U.S.A and Japan. Korea is developing HDTV system. HDTV system manipulates and communicates digital data between camera & broadcasting system in contrast to NTSC TV system. These Data are composed of 20 bits, 74.25 Mwords/s. Transmitter serializes these parallel data to 1.485 Gb/s serial data. Receiver deserializes 1.485 Gb/s serial data to original 20 bits, 74.25 Mwords/s parallel data. Most GHz network communication chip is made of GaAs or Bipolar because of large transconductance and high unit gain frquency. Although CMOS has small transconductance and low unit gain frequency, in this paper we want design receiver using CMOS process for low cost and mass production. Receiver chip is composed of clock and data recovery circuit and Demux. This chip is designed in 0.8 um CMOS. Clock and data recovery circuit is based upon the guadricorrelator architecture that the capture range is about 900MHz. For input noise immunity improvement loop gain control is used. Demux is composed of three 1:2 Demux and four 1:5 shift register type Demux. This mixed type DeMux can deserialize any parallel data with even bits without any dummy cells. Total power consumption is about 1 W from a +5V power supply.

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