In this paper, the switch-level fault simulator for CMOS circuits with a gate-to-drain/source short fault is implemented. A fault model used in this paper is based on the graphical analysis of the electrical characteristics of the faulty MOS devices and the conversion of the faulty CMOS circuit to the equivalent faulty CMOS inverter in order to find its effect on the successive stage. This technique is very simple and has the increased accuracy of the simulation. The simulation result of the faulty circuit using the implemented fault simulator is compared with the result of the SPICE simulation.
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