It is very common in today 's design practice to simulate a big design with a large set of test vectors thereby generating a huge set of data (simulation results) to be analyzed. As the design grows, the simulation results grow and become harder to handled. In this paper, we present algorithms for the compression and regeneration of simulation results. The compression is performed by sampling nets in a circuit. If the user wants to examine the lost part of the data, it is quickly regenerated by applying incremental simulation technique. Experimental results obtained for several practical circuits show that the compression ratio of 10 is easily obtained while maintaining a reasonably fast regeneration of data on a 15.7 MIPS workstation. Using the proposed method we can effectively reduce debug cycle time.
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