VHDL simulation requires both analysis and elaboration processes. Reducing the time taken by these processes shorten design cycles. We propose an incremental analysis and elaboration algorithm for VHDL, which minimizes the number of design units to be re-analyzed and re-elaborated after an incremental change, thereby reducing the desing cycle time. Experimental results show about four times performance improvement in analysis and 1.25 times in elaboration over the conventional method.
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