최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기한국해양정보통신학회논문지 = The journal of the Korea Institute of Maritime Information & Communication Sciences, v.10 no.2, 2006년, pp.321 - 327
, , 노영욱 (신라대학교 컴퓨터교육과)
This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSi...
* AI 자동 식별 결과로 적합하지 않은 문장이 있을 수 있으니, 이용에 유의하시기 바랍니다.
A. P. Chandrakasan, S. Sheng and R. W. Brodersen, 'Low Power CMOS Digital Design,' IEEE Journal of Solid State Circuits, Vol. 27, No.4, pp. 473-483, April 1992
Chip Weems, ''http://www.cs.umass.edu/-weems/researeh_ talks/Real-Time_RISC/index.htm,' Techinical Research Presentation September 1998
www.arm.com, 'Techinical Reference Manual,' pp. 35-122, April-2001
Charles Severance, http://www.netfact.cotn/-crs /faculty/ann1996.html, 'Beyond RISC- The Post RISC Architecture' - MIT Lincoln Labs, May 20, 1996
Mutoh Shin'ichiro, Takakuni Douseki, Yasukuki matsuya, Takahiro Aoki, Santoshi Shigermatsu, Junzo Yamada, '1-V Power Supply high Speed Digital Circuit Technology With Multithreshold Voltage CMOS,' IEEE Journal of Solid State Circuits, Vol. 30,No.8, pp. 847-854, August 1995
Agarwal Ankur, Pandya Abhijit, Folleco Andres, 'A Novel Low Power Design of an ALU,' CCCIT Conference of Microprocessors, July2003
K. Yano eI at., 'A 3.8ns CMOS 16*16 Multiplier using Complementary Pass Transistor logic,' IEEE Journal of Solid State Circuit, Vol.25, pp 388-395, April 1990
JU. Wang. S.Fang and W.Feng, 'New Efficient Designs for XOR and XNOR functions on Transistor Level,' IEEE Journal of Solid State Circuits, Vol.29,No. 7, pp.780-786, July 1994
R. Shalem,E. John, L. K. John, 'A Novel Low Power Energy Recovery Full AdderCell,' Proceedings of the IEEE Great Lakes Symposium of VLSI, pp. 380-383, February 1999
Nagendra, M. J. Irwin and R.M.Owens, 'Area Time-Power- Tradeoff in Parallel Adders,' IEEE Circuits and System II, Vol 43, No. 10, pp 689-702, 1996
A. Agarwal, 'Low Power Design of an ALU,' MS Thesis, Florida Atlantic University, August 2003
N. Weste and Eshraghian, Principles of CMOS VLSI Design, A System Perspective, MA Addision- Wesley, 1993
K. Yano, 'Top Down Pass Transistor Logic Design,' IEEE Journal of Solid State Circuits, Vol. 32 No.7, pp. 1079-1089,1997
R. Zimmermann and W. Fichtner, 'Low Power Logic Styles: CMOS Versus Pass- Transistor Logic,' IEEE Joumal of Solid State Circuits, Vol.32,pp. 1079-1089, 1997
Pandya Abhijit, Ankur Agarwal, P. K. Kim,' Low Power Design of a Neuro processor,' Knowledge-Based lntelligent Information and Engineering Systems, Eds. V. Palade, R.J. Howlett and L. Jain, Springer, Berlin, Vol.2 pp.856-862, 2003
L.J.M.Veendrick, 'Short Circuit Dissipitaion of CMOS Circuitry and its Impact on the design of the buffer circuits,' IEEE journal of Solid State Circuits, Vol. SC-19, pp. 468-473, August 1984
A. Al-Sheraidah, 'Novel Multiplexer- Based Architecture for Full Adder Design,' MS Thesis, Florida Atlantic University, August 2000
J. M. Rabaey, Digital Integrated Circuits, A Design Perspective, Prentice Hall, 1995
A. P. Chandrakasan, S. Sheng and R. W. Brodersen, 'Low Power CMOS Digital Design,' IEEEJoumal of Solid State Circuits, Vol.27, No.4, pp. 473-483, April 1992
*원문 PDF 파일 및 링크정보가 존재하지 않을 경우 KISTI DDS 시스템에서 제공하는 원문복사서비스를 사용할 수 있습니다.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.