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논문 상세정보

3-Dimensional Numerical Analysis of Deep Depletion Buried Channel MOSFETs and CCDs

Abstract

The visual analysis of buried channel (Be) devices such as buried channel MOSFETs and CCDs (Charge Coupled Devices) is investigated to give better understanding and insight for their electrical behaviours using a 3-dimensional (3-D) numerical simulation. This paper clearly demonstrates the capability of the numerical simulation of 'EVEREST' for characterising the analysis of a depletion mode MOSFET and BC CCD, which is a simulation software package of the semiconductor device. The inverse threshold and punch-through voltages obtained from the simulations showed an excellent agreement with those from the measurement involving errors of within approximately 1.8% and 6%, respectively, leading to the channel implanted doping profile of only approximately $4{\sim}5%$ error. For simulation of a buried channel CCD an advanced adaptive discretising technique was used to provide more accurate analysis for the potential barrier height between two channels and depletion depth of a deep depletion CCD, thereby reducing the CPU running time and computer storage requirements. The simulated result for the depletion depth also showed good agreement with the measurement. Thus, the results obtained from this simulation can be employed as the input data of a circuit simulator.

참고문헌 (17)

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  8. M.H. Kim and S.H. Lim, 'Three dimensional numerical simulation of buried channel MOSFETs,' ICEIC 2000 Proceedings of The 2000 International Conference on Electronics, Information and Communication, pp. 453- 456, August 9-11, 2000, Shenyang, China 
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  16. K. J. McCarthy and A. Wells, 'Measurement and simulation of X-ray quantum efficiency and energy resolution of large area CCDs between 0.3 and 10keV' SPIE Vol. 1743 EUV, X-RAY, and Gamma- Ray Instrumention for Astronomy III 1992 
  17. M.H. Kim and S.H. Lim, 'Three dimensional Characterizing Analysis of Astronomic CCDs with a Deep Depletion,'Proceedings of the Optical Society of Korea Summer Meeting 2000, pp. 228-229, August 17-18, 2000, JinJu, Korea 

이 논문을 인용한 문헌 (1)

  1. 2007. "" Journal of electrical engineering & technology, 2(4): 518~524 

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