선택한 단어 수는 입니다.
최소 단어 이상 선택하여야 합니다.
최소 단어 이상 선택하여야 합니다.
선택한 단어 수는 30입니다.
최대 10 단어까지만 선택 가능합니다.
최대 10 단어까지만 선택 가능합니다.
제안 방법
- The mitigation options are made by setting resistors R4, R5, R7, and R8 identically to 100KΩ for ‘MAG_OPC’, to 75 KΩ, 125 KΩ, 125 KΩ, and 75 KΩ for ‘MAG_OPL’, and to 125 KΩ, 75 KΩ, 75 KΩ, and 125 KΩ for ‘MAG_OPH’, respectively.
- For read operation, after VSDL is precharged to VPRE with S0 turned on, IREF is injected to VSDL with S1 turned on for developing a voltage difference between VSDL and VREFSA, which is made by the current difference between the cell read current and IREF. Then, the voltage comparator detects whether the VSDL is higher or lower than VREFSA to evaluate the output data.
대상 데이터
- Phase-change random access memory (PRAM) has been emerged as a next-generation memory due to excellent scalability, non-volatility, and random accessibility. A PRAM cell is made of resistive material, Ge2Sb2Te5 (GST) [1, 2]. When GST is injected with high current for being heated above the melting point and then cooled down fast, the lattice structure becomes amorphous.
- 5 compares IREF versus trimming code values for the conventional and proposed schemes identically in 7-bit resolution. Resistors, R2, R3, R4, R5, R7, and R8, in the proposed circuit are identically set to be at 100 KΩ as the base design. The evaluation result in Fig.
- 3 shows the proposed read-sensing reference current generation circuit with an accurate adaptive resolution control. The circuit is composed of an N-bit level trimmer, an adaptive resolution converter, a voltage-to-current converter, and extra circuits including pads for identifying and monitoring the target IREF level. For a fine resolution control with wide tuning range, a voltage control method is adopted instead of the current control method used in the conventional scheme.
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