최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기情報保護學會論文誌 = Journal of the Korea Institute of Information Security and Cryptology, v.31 no.3, 2021년, pp.473 - 480
To achieve the high-speed implementation of post-quantum cryptography, primitive operations should be tailored to the architecture of the target processor. In this paper, we present the optimized implementation of multiplier operation on RISC-V processor for post-quantum cryptography. Particularly, ...
K. Asanovic, and A. Waterman, "The RISC-V Instruction Set Manual. In Privileged Architecture," RISC-V Foundation, 2(1), pp. 1-91, May. 2017.
E. Alkim, H. Evkan, N. Lahr, R. Niederhagen, R. Petri, "ISA Extensions for Finite Field Arithmetic," IACR Transactions on Cryptographic Hardware and Embedded Systems, pp. 219-242, Aug. 2020.
B. Marshall, G. R. Newell, D. Page, M. J. O. Saarinen, and C. Wolf, "The design of scalar AES Instruction Set Extensions for RISC-V," IACR Transactions on Cryptographic Hardware and Embedded Systems, pp. 109-136, Aug. 2021.
K. Stoffelen, "Efficient cryptography on the RISC-V architecture. In International Conference on Cryptology and Information Security in Latin America, pp. 323-340, Oct. 2019.
S. van den Berg, "RISC-V implementation of the NaCl-library," Master Thesis, 1(1), pp. 1-52, 2020.
A. Adomnicai, and T. Peyrin, "Fixslicing AES-like Ciphers," IACR Transactions on Cryptographic Hardware and Embedded Systems, pp. 402-425, Aug. 2021.
M. R. Albrecht, C. Hanser, A. Hoeller, T. Poppelmann, F. Virdia, A. Wallner, "Implementing RLWE-based schemes using an RSA co-processor," IACR Transactions on Cryptographic Hardware and Embedded Systems, pp. 169-208, Aug. 2019.
H. Seo, Z. Liu, P. Longa, and Z. Hu, "SIDH on ARM: faster modular multiplications for faster post-quantum supersingular isogeny key exchange," IACR Transactions on Cryptographic Hardware and Embedded Systems, pp. 1-20, Aug. 2018.
H. Seo, R. Azarderakhsh, "Curve448 on 32-Bit ARM Cortex-M4," In International Conference on Information Security and Cryptology, pp. 125-139, Dec. 2020.
P. G. Comba, "Exponentiation cryptosystems on the IBM PC," IBM systems journal, 29(4), pp. 526-538, 1990.
H. Seo, H. Kim, "Multi-precision multiplication for public-key cryptography on embedded microprocessors," In International Workshop on Information Security Applications, pp. 55-67, Aug. 2012.
H. Seo, P. Sanal, R. Azarderakhsh, "SIKE in 32-bit ARM Processors Based on Redundant Number System for NIST Level-II," ACM Transactions on Embedded Computing Systems (TECS), 20(3), pp. 1-23, 2021.
H. Seo, Z. Liu, Y. Nogami, T. Park, J. Choi, L. Zhou, H. Kim, "Faster ECC over F_{2^{521}-1} (feat. NEON)," In ICISC 2015, pp. 169-181, Dec. 2015.
H. Seo, "Memory efficient implementation of modular multiplication for 32-bit ARM Cortex-M4," Applied Sciences, 10(4), pp. 1539, 2020.
*원문 PDF 파일 및 링크정보가 존재하지 않을 경우 KISTI DDS 시스템에서 제공하는 원문복사서비스를 사용할 수 있습니다.
Free Access. 출판사/학술단체 등이 허락한 무료 공개 사이트를 통해 자유로운 이용이 가능한 논문
※ AI-Helper는 부적절한 답변을 할 수 있습니다.