Abstract

Yield analysis and improvement is critical for IC manufacturing companies to reduce cost and remain competitive in the market. This paper uses a combined data mining and data visualization technique to extract useful information from data collected from a quality engineering engagement during IC manufacturing process called Lot In-line Process Control (LPC). The yield rates of lots are first classified into two categories: high and low, according to a threshold recommended by customers. Then a binary decision tree is generated from the input LPC data to find features that classify a subset of lots into the same class. Although rules collected from decision trees generated under different parameter settings provide useful guidelines to analyze the causing factors of low-yielding wafers, it is not easy to examine large number of rules represented in text or tabular format. To solve the rule interpretation problem, we display rules as polygonal lines in a N-dimensional data visualization scheme called parallel coordinates. The visual image enables users to quickly spot patterns that are difficult to be found by text reading. The combined data mining and data visualization approach provides process engineers a more subjective basis to study the causing factors of low-yielding wafers, in contrast to the more objective basis originally employed such as the domain knowledge and past experiences.

주제어

#IC manufacturing   #data mining   #decision tree   #data visualization   #parallel coordinates  

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