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NTIS 바로가기Solid-state electronics, v.136, 2017년, pp.81 - 85
Woo, Changbeom (Inter University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-744, South Korea) , Ko, Kyul (Inter University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-744, South Korea) , Kim, Jongsu (Inter University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-744, South Korea) , Kim, Minsoo (Inter University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-744, South Korea) , Kang, Myounggon (Department of Electronics Engineering, Korea National University of Transportation, Chungju-City 380-702, South Korea) , Shin, Hyungcheol (Inter University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-744, South Korea)
In this paper, we have analyzed short channel effects (SCEs) and RC delay with Vertical nanoplate FET (VNFET) using 3-D Technology computer-aided design (TCAD) simulation. The device is based on International Technology Road-map for Semiconductor (ITRS) 2013 recommendations, and it has initially gat...
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