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NTIS 바로가기Facta universitatis. Series Electronics and energetics, v.16 no.2, 2003년, pp.215 - 232
Jovanovic, Goran (Faculty of Electronic Engineering, University of Niš) , Stojcev K., Mile
This paper describes dual delay locked loop architecture with a mixed mode phase tuning method. The circuit accomplishes low jitter, unlimited phase shift in a large operating range, and accurate phase alignment with high resolution for relatively low input clock frequency. The architecture employs ...
Taylor, S.S.. A high-performance GaAs pin electronics circuit for automatic test equipment. IEEE journal of solid-state circuits, vol.28, no.10, 1023-1029.
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