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Method and apparatus for encoding data and clock information in a self-clocking data stream

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H04L-007/00
출원번호 US-0555520 (1975-03-05)
발명자 / 주소
  • Dobias Joseph J. (Poway CA)
출원인 / 주소
  • NCR Corporation (Dayton OH 02)
인용정보 피인용 횟수 : 53  인용 특허 : 0

초록

A method and apparatus is described for generating a data stream incorporating a self-clocking Manchester type code. The data, originally stored in a shift register, is shifted out of the register in bi-level form with a first voltage level representing one binary value and a second voltage level re

대표청구항

A method of encoding and transmitting binary information, represented by a wave form having a first voltage level during a bit period indicating one binary value and a second voltage level during a bit period indicating a second binary value, into a bi-phase self-clocking bit stream, comprising the

이 특허를 인용한 특허 (53)

  1. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  2. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  3. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  4. Ramchandran, Amit, Adaptable datapath for a digital processing system.
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
  9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
  10. Prucnal Paul R. (New York NY) Perrier Philippe A. (Viroflay FRX), Alternate mark/space inversion line code.
  11. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.
  12. Dingeman Drake D. (Springfield OH), Apparatus and method for binary data transmission.
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.
  16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
  17. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
  18. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.
  19. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
  20. Tucker John F. (San Diego CA), Data acquisition and transfer system.
  21. Groves Stanley E. (Round Rock TX), Digital logic for separating data and clock in Manchester-encoded data.
  22. Scheuermann,Walter James, Hardware implementation of the secure hash standard.
  23. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  24. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  25. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  26. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  27. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.
  28. Saltzberg Burton R. (Middletown NJ), Manchester code receiver.
  29. Khoudari Benjamin M. (Great Neck NY), Manchester decoder.
  30. Demange Jean-Pierre (Strasbourg FRX) Lagarde Pierre (Dingsheim FRX), Method and apparatus for coding and decoding binary data.
  31. Johnson ; III Hoke S. (Monte Sereno CA), Method and circuit for decoding a Manchester code signal.
  32. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
  33. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
  34. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  35. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  36. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  37. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.
  38. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  39. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  40. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  41. Scheuermann, W. James, Method and system for reconfigurable channel coding.
  42. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.
  43. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.
  44. Chi Chao S. (San Diego CA), Self clocking binary data encoding/decoding method.
  45. Murdock, Gary Steven, Self-clocked two-level differential signaling methods and apparatus.
  46. Arndt Richard Louis (Byron MN) Teal Thomas Richard (Rochester MN), Self-clocking data entry unit system.
  47. Glenn L. Richards, Serial line synchronization method and apparatus.
  48. Richards Glenn L., Serial line synchronization method and apparatus.
  49. Eastmond ; Bruce C., Split phase code synchronizer and demodulator.
  50. Master,Paul L.; Watson,John, Storage and delivery of device features.
  51. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.
  52. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.
  53. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
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