초록 ▼

A programmable logic controller has input elements sampled to determine status in each of multicomponent lines of a relay ladder network. Output elements in the network connect power voltage sources to power utilization units and disconnect the same in accordance with a programmed set of instruction

A programmable logic controller has input elements sampled to determine status in each of multicomponent lines of a relay ladder network. Output elements in the network connect power voltage sources to power utilization units and disconnect the same in accordance with a programmed set of instructions stored in a controller memory to satisfy operating conditions required of the ladder network. Sample means sequentially generate a set of one bit words, one word representing the state of each of the input elements. A set of one bit output control states is generated, one state for each output element in dependence upon the states of the input elements. Timing means operable once each half cycle of the power voltage initiates generation and storage in a semiconductor read/write image register of one bit input words and output control states. Further, the timing means includes control means for sequentially instituting a serial I/O mode in which the input elements are sampled and the output states are read out of the register and applied to the output elements followed by a run mode in which a new set of control states is established and stored in the register.

대표청구항 ▼

In a programmable controller for selectively connecting and disconnecting an alternating current power signal to each of m output devices in response to computed respective on/off states generated by execution of a control program stored in a memory means on n binary parameters, wherein the value of

In a programmable controller for selectively connecting and disconnecting an alternating current power signal to each of m output devices in response to computed respective on/off states generated by execution of a control program stored in a memory means on n binary parameters, wherein the value of each of said parameters corresponds to the on/off state of a respective input device, the combination which comprises: a. a readable and writable image register having at least m +n single bit storage locations for temporarily storing a set of said n binary parameters and a set of on/off states for said m output devices; b. timing means responsive to said alternating current power signal for generating an initiate input/output control signal once each half cycle of said power signal; c. means coupled to said timing means and responsive to said initiate input/output control signal for writing and reading single bit words into and out of said image register, said means including: i. sampling means for sampling the on/off states of said n input devices and generating a set of n respective single bit binary parameters corresponding to the on/off state of said input devices when an initiate input/output control signal is received; ii. first transfer means for serially writing said n single bit binary parameters generated by said sampling means into said image register; and iii. second transfer means for serially reading m single bit previously computed on/off states for said output devices out of said image register means for transmission to said output devices; and d. computing means coupling to said memory means and to said image register and responsive to said control program and to said single bit binary parameters for computing the on/off statEs of the output devices.