초록 ▼

A resolver to digital converter which provides digitally generated sinusoidal voltages to apply to the stator windings of the resolver. The oscillator providing the digital pulses is connected to a counter which is reset on a particular phase of one of the stator winding voltages. The output of the

A resolver to digital converter which provides digitally generated sinusoidal voltages to apply to the stator windings of the resolver. The oscillator providing the digital pulses is connected to a counter which is reset on a particular phase of one of the stator winding voltages. The output of the counter is transferred into an output register at a particular phase of the rotor voltage with the output register thereby providing a digital reading of the angular position of the rotor. Digital comparator means are provided for insuring that the stator voltages remain exactly 90°out of phase, and further means are provided for insuring that the stator voltages remain at the same amplitude.

대표청구항 ▼

A resolver to digital converter comprising a high frequency signal source; a frequency divider connected to said source, said divider providing a low-frequency signal; first and second filtering means for converting a low-frequency signal to a sinusoidal signal, each of said filtering means having a

A resolver to digital converter comprising a high frequency signal source; a frequency divider connected to said source, said divider providing a low-frequency signal; first and second filtering means for converting a low-frequency signal to a sinusoidal signal, each of said filtering means having an input and an output, said input of said first filtering means being connected to the output of said divider; a resolver having first and second stator windings and a rotor winding; said first stator winding being connected to said output of said first filtering means; first, second and third zero crossing detectors each having an input and an output, said input of said first detector being connected to said output of said first filtering means; a binary counter having a signal input, a reset input and a plurality of output leads, said signal input lead of said binary counter being connected to said high frequency signal source, said reset input lead being connected to said output of said first detector, said first detector providing a pulse to reset said binary counter at the end of each cycle of said sinusoidal signal; an up/down counter having first and second input leads for adding and subtracting to the count in said up/down counter and a plurality of output leads; first and second logic gates each having first, second and third input leads and an output lead, said output of said second zero crossing detector being connected to said first input lead of said first gate, a flip-flop, said flip-flop being connected between a first output lead of said binary counter and a second input lead of each of said first and said second gates, said output lead of said first gate being connected to said first input lead of said up/down counter; an inverter, said inverter being connected between said output of said second zero crossing detector and said first input lead of said second gate, said high frequency source being connected to said third input lead of each of said first and said second gates, said output lead of said second gate being connected to said second input lead of said up/down counter; a comparator having an output lead, said output leads of said binary counter and of said up/down counter being connected to said comparator, said comparator providing a pulse to said output lead each time the count of said binary counter matches the count of said up/down counter, said output lead of said comparator being coupled to said input of said second filtering means, said output of said second filtering means being connected to said second stator winding and to said input lead of said second zero crossing detector; and an output register having a plurality of signal input leads and a trigger input lead, said signal input leads of said register each being connected to a corresponding one of said output leads of said binary counter, said trigger input lead of said register being connected to said output of said third detector, said input of said third detector being connected to said rotor winding of said resolver.