초록 ▼

Matched voltage-controlled resistances are provided across the drain-to-source channels of a pair of FET\s, each FET having a gate electrode connected through an associated control resistor to the same one terminal of a source of DC control voltage; having a source electrode electrically connected t

Matched voltage-controlled resistances are provided across the drain-to-source channels of a pair of FET\s, each FET having a gate electrode connected through an associated control resistor to the same one terminal of a source of DC control voltage; having a source electrode electrically connected to the same other terminal of the voltage source; and having an associated feedback resistor electrically connected between its drain and gate electrodes. The drain electrodes are preferably capacitively coupled to input or output terminals to prevent DC loading of the FET network by external circuitry. A resistor is also connected across the drain-to-source channel of each FET to limit the maximum value of net resistance presented thereby. The resistance of one of the control resistors is adjusted to have a value which causes the net drain-to-source resistance of the associated FET to have the same value as that of the other FET for a particular value of control voltage. The net drain-to-source resistances of the two FET\s are then closely matched over a range of control voltages.

대표청구항 ▼

Apparatus providing first and second voltage-controlled resistances between associated first and second pairs of nodes thereof which are matched over a range of control voltages, comprising: first and second field effect transistors (FET\s) having gate electrodes, having drain electrodes electricall

Apparatus providing first and second voltage-controlled resistances between associated first and second pairs of nodes thereof which are matched over a range of control voltages, comprising: first and second field effect transistors (FET\s) having gate electrodes, having drain electrodes electrically connected to first nodes of associated first and second pairs of nodes, and having source electrodes electrically connected to second nodes of associated first and second pairs of nodes, each of said FET\s having a drain-to-source channel resistance that is variable as a function of a voltage that is applied across one of the gate-to-source and gate-to-drain channels thereof; a source of DC control voltage having first and second terminals; means electrically connecting the first terminal of said voltage source to one of the source and drain electrodes of each of said FET\s and electrically connecting the second terminal of said voltage source to the gate electrode of said first FET; a first resistor electrically connected across the channel of said second FET gate electrode and the other one of the source and drain electrodes of said second FET; and a second resistor electrically connected between the second terminal of said voltage source and the gate electrode of said second FET, said second resistor having a resistance causing the resistances across the first and second pairs of nodes to be the same value for a prescribed common control voltage measured across the terminals of said voltage source and causing the resistance across the second pair of nodes to be substantially equal to the resistance across the first pair of nodes over a range of control voltages.