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Pipe line high speed signal processor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-007/38
  • G06F-015/00
출원번호 US-0454339 (1974-03-25)
발명자 / 주소
  • Lynch
  • Jr. David D. (Northridge CA) Tower Lee W. (Los Angeles CA)
출원인 / 주소
  • Hughes Aircraft Company (Culver City CA 02)
인용정보 피인용 횟수 : 68  인용 특허 : 0

초록 ▼

Control for overlapping instruction execution in an arithmetic unit is provided by stepping a sequence of instructions through a plurality of registers connected in cascade and separately decoding each instruction in a register for control of a corresponding stage in one or more data processing path

대표청구항 ▼

A synchronous data processor having a source of synchronizing clock pulses and multiple paths for processing instructions and data comprising an instruction path including a chain of instruction registers including a first and a last instruction register with all of said instruction registers couPle

이 특허를 인용한 특허 (68)

  1. Alexander, Khary J.; Busaba, Fadi Y.; Curran, Brian W.; Hutton, David S.; Malley, Edward T.; Prasky, Brian R.; Rell, Jr., John G., Accelerated execution of execute instruction target.
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  2. Alexander, Khary J.; Busaba, Fadi Y.; Curran, Brian W.; Hutton, David S.; Malley, Edward T.; Prasky, Brian R.; Rell, Jr., John G., Accelerated execution of target of execute instruction.
    상세보기
  3. Kindseth Douglas M. (Stewartville MN) Mitchell Glen R. (Pine Island MN), Access-time reduction control circuit and process for digital storage devices.
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  9. Bowling, Stephen A., Configuration fuses for setting PWM options.
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  10. Fukunaga Yasushi (Hitachi JPX) Bandoh Tadaaki (Hitachi JPX), Control of instruction pipeline in data processing system.
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  11. Leymann, Frank; Roller, Dieter, Controlling the creation of process instances in workflow management systems.
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  12. Jones Walter A. (Chelmsford MA) Jones ; Jr. Paul R. (Northboro MA) Papworth David B. (Framingham MA), Data processing apparatus and method employing instruction flow prediction.
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  13. Dennis Jack B. (Belmont MA) Misunas David P. (Brighton MA), Data processing apparatus for highly parallel execution of stored programs.
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  14. Iwashita Masao (Tokyo JPX) Tenma Tsutomu (Tokyo JPX), Data processing machine suitable for high-speed processing.
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  15. Iwashita Masao (Tokyo JPX) Tenma Tsutomu (Tokyo JPX), Data processing machine suitable for high-speed processing.
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  16. Tanakura Yoshiyuki (Numazu JPX) Uchida Keiichiro (Kawasaki JPX), Data processing system having a high speed pipeline processing architecture.
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  17. Matsumoto Hidekazu (Hitachi JPX) Bandoh Tadaaki (Ibaraki JPX) Maejima Hideo (Hitachi JPX), Data processing unit with pipelined operands.
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  18. Zolnowsky John (Austin TX) MacGregor Douglas B. (Austin TX) Eckert Kim (Downingtown PA), Data processor which can repeat the execution of instruction loops with minimal instruction fetches.
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  19. Catherwood,Michael I., Dual mode arithmetic saturation processing.
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  20. Catherwood, Michael I., Euclidean distance instructions.
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  21. Yamazaki Isamu (Kawasaki JPX), Index limited continuous operation vector processor.
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  23. Pennock, James D.; Baker, Ronald; Parker, Brian R.; Belcher, Christopher, Interleaved hardware multithreading processor architecture.
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  24. Sproul ; III William W. (Reston VA), Interrupt processor.
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  25. Pomerene James H. (Chappaqua NY), Machine for multiple instruction execution.
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  26. Deao Douglas E. ; Seshan Natarajan ; Lell Anthony J., Maintaining synchronism between a processor pipeline and subsystem pipelines during debugging of a data processing syst.
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  27. Catherwood, Michael I., Maximally negative signed fractional number multiplication.
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  28. Vrba ; Richard Alan, Memory control structure for a pipelined mini-processor system.
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  29. MacDougall James R. (Plano TX) Richter David L. (Plano TX), Memory unit with pipelined cycle of operations.
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  30. Jen Amy K. (Vestal NY) Ngai Agnes Y. (Endwell NY), Method and apparatus for compressing the execution time of an instruction stream executing in a pipelined processor.
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  31. Langdon ; Jr. Glen G. (San Jose CA), Method and means for pipeline decoding of the high to low order pairwise combined digits of a decodable set of relativel.
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  32. Takesue, Masaru, Microprogrammed, multipurpose processor having controllable execution speed.
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  33. Catherwood,Michael, Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection.
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  36. Berkovich Semyon ; Berkovich Efraim ; Loew Murray H., Multi-layer multi-processor information conveyor with periodic transferring of processors' states for on-the-fly transformation of continuous information flows and operating method therefor.
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  38. Eisenhard, Bruce T.; Smith, Stephen R.; Sander, Wendell B., Multiprocessor intelligent cell for a network which provides sensing, bidirectional communications and control.
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  43. Ishii Hideshi (Tokyo JPX), Pipeline-controlled data processing system capable of performing a plurality of instructions simultaneously.
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  45. Eaton John R. (Salford GB2), Pipelined data processing system with centralized microprogram control.
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  49. Bowling, Stephen A., Processor with dual-deadtime pulse width modulation generator.
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  50. Gilbert Laurenti FR, Processor with instruction qualifiers to control MMU operation.
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  51. Miller Gary I. (Los Angeles CA), Programmable arithmetic logic unit.
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  52. Kusakabe Hiroyuki (Tokyo JPX), Programmable controller with timing control.
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  53. Catherwood,Michael I., Reduced power option.
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  54. Cook, Neal Andrew; Wootton, Alan T.; Peterson, James, Reducing data hazards in pipelined processors to provide high processor utilization.
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  57. Crook, Neal Andrew; Wootton, Alan T.; Peterson, James, Reducing data hazards in pipelined processors to provide high processor utilization.
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  58. Kassabov Nikola K. (Sofia BGX) Dakovski Lyudmil G. (Sofia BGX), Register arithmetic device.
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  59. Catherwood, Michael; Triece, Joseph W., Repeat instruction with interrupt.
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  60. Elliott,John, Sticky z bit.
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  61. Kitamura Toshiaki (Tokyo JPX) Oinaga Yuji (Tokyo JPX) Onishi Katsumi (Kawagoe JPX), System for by-pass control in pipeline operation of computer.
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  62. Gupta Ram K. (Downington PA) Vora Chandrakant R. (Audubon PA), Template micromemory structure for a pipelined microprogrammable data processing system.
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  63. Riffe Josephus (Plantation FL) Rice Richard (West Palm Beach FL), Token generator.
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  64. Boles,Brian; Triece,Joseph W.; Conner,Joshua M., Variable cycle interrupt disabling.
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  65. Lahti Archie E. (Fridley MN), Vector data logical usage conflict detection.
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  66. Omoda Koichiro (Hadano JPX) Nagashima Shigeo (Hachioji JPX) Torii Shunichi (Kokubunji JPX), Vector data processor.
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  67. Drimak Edward G. (Johnson City NY), Vector processing.
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  68. Yoshida Yaoko (Tokyo JPX), Vector processing apparatus including means for identifying the occurrence of exceptions in the processing of vector ele.
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