초록 ▼

A signal analyzer system is disclosed which includes an arithmetic processor containing a plurality of pipeline processor elements in parallel array with each element connected to a respective working store, with all of the elements being under microprogram control of an arithmetic element controlle

A signal analyzer system is disclosed which includes an arithmetic processor containing a plurality of pipeline processor elements in parallel array with each element connected to a respective working store, with all of the elements being under microprogram control of an arithmetic element controller. A storage controller included in the system is connected to the arithmetic processor, to a system input and to a system ouput. A bulk storage included in the system is connected to the storage controller. The storage controller controls data transfers into and out of the system and between the bulk storage and arithmetic processor. A control processor included in the system is connected to the arithmetic processor and the storage controller by means of a data bus for centrally controlling the operation of the plurality of pipeline processor elements by transmitting micro control words over the bus.

대표청구항 ▼

A digital computer system comprising: an arithmetic processor containing a plurality of pipelined processor arithmetic elements in parallel array with each element connected to a respective working store for temporarily storing data, with all of the elements being connected to and under microprogram

A digital computer system comprising: an arithmetic processor containing a plurality of pipelined processor arithmetic elements in parallel array with each element connected to a respective working store for temporarily storing data, with all of the elements being connected to and under microprogram control of an arithmetic element controller, for arithmetically processing said data; said arithmetic element controller including an arithmetic element control store for storing arithmetic element microinstructions and a memory address register connected to an address input of said arithmetic element control store for accessing said arithmetic element microinstruction; a bulk store for storing said data and said arithmetic element microinstructions prior to the time of an initial microprogram load into said arithmetic processor; a storage controller connected to said bulk store and to said working store and said arithmetic element control store in said arithmetic processor for selectively transferring said arithmetic element microinstructions from said bulk store to said arithmetic element control store in response to a first transfer command word and selectively transferring said data from said bulk store to said working store in response to a second transfer command word; a control processor connected to an input of said memory address register in said arithmetic element controller and to said storage controller by means of an external bus, for sending said first transfer command word to said storage controller at said initial microprogram load time to load said microinstructions into said control store, for sending a first control store address to said memory address register after said load time to initiate execution by the microprogram in said arithmetic processor, and for subsequently sending said second transfer command word to said storage control during execution time, to transfer said data to said working store; whereby the control processor is free to carry out supervisory and data management functions during said execution time and the program storage and data storage functions are separated during execution time, minimizing storage bandwidth requirements.