Cooper Leon N. (Providence RI) Elbaum Charles (Providence RI)
출원인 / 주소
Nestor Associates (Stonington CT 02)
인용정보
피인용 횟수 :
33인용 특허 :
1
초록▼
A digital adaptive information processing system which executes the algorithm described in our U.S. Pat. No. 3,950,733 issued April 13, 1976. The system includes a digital input register adapted to receive and store N numbers s1, s2, . . . sN representing an input signal; a digital output register a
A digital adaptive information processing system which executes the algorithm described in our U.S. Pat. No. 3,950,733 issued April 13, 1976. The system includes a digital input register adapted to receive and store N numbers s1, s2, . . . sN representing an input signal; a digital output register adapted to receive and store n numbers r1, r2, . . . rn representing an output response; and digital information processing apparatus, connecting the input register with the output register, and operative to carry out the processing steps required to “map”the numbers stored in the input register into numbers placed in storage in the output register in accordance with the aforementioned algorithm.
대표청구항▼
A digital, adaptive information processing system comprising, in combination: a. digital input register means for storing a plurality (N) of digital numbers s1, s2. . . sj, . . . sN, representing an input signal; b. digital output register means for storing a plurality (n) of digital numbers r1, r2.
A digital, adaptive information processing system comprising, in combination: a. digital input register means for storing a plurality (N) of digital numbers s1, s2. . . sj, . . . sN, representing an input signal; b. digital output register means for storing a plurality (n) of digital numbers r1, r2. . . ri, . . .rn, representing an output response; and c. digital information processing apparatus connecting said input register means with said output register means, said apparatus comprising: 1. digital memory means for storing a plurality (n ×N) of digital weighting numbers A11, A12. . .Aij, . . . AnN; 2. digital multiplier means, coupled to said input register means and to said memory means, for multiplying selected ones sj of said numbers located in said input register means with selected ones Aij of said weighting numbers to produce digital product numbers s′j in accordance with the formula: s′j =Aijsj; 3. digital adder means, coupled to said multiplier means and to said output register means, for adding together selected ones of said product numbers s′j produced by said multiplier means to produce digital sum numbers ri in accordance with the formula: [Figure] said sum numbers ri being stored in said output register means; and 4. digital modifier means, coupled to said input register means, said output register means and to said memory means, for changing at least one of said weighting numbers Aij in accordance with the formula: Aij(t) =gAij(t-1) +hsjri; where Aij(t) is the new number stored in said memory means, Aij(t-1) is the number previously stored in said memory means, go≤g ho≤hsjis the number stored in said input register means, ri is the member stored in said output register means, and i and j are integers from 1 to n and N, respectively.
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이 특허에 인용된 특허 (1)
Cooper Leon N. (Providence RI) Elbaum Charles (Providence RI), Information processing system.
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Hoffberg, Steven M; Hoffberg-Borghesani, Linda I, Mobile system, a method of operating mobile system and a non-transitory computer readable medium for a programmable control of a mobile system.
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