초록 ▼

A digital system comprises a plurality of metal-oxide-semiconductors (MOS) chip random access memory (RAM) and read only memory (ROM) and peripheral interface adaptor circuits used as part of the computer coupled to a common bidirectional data bus which is coupled to and controlled by a microprocess

A digital system comprises a plurality of metal-oxide-semiconductors (MOS) chip random access memory (RAM) and read only memory (ROM) and peripheral interface adaptor circuits used as part of the computer coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU) chip. In the digital system, data transfers on the common bidirectional data bus are accomplished without the use of a memory synchronization signal so that a special signal conductor indicating when the memory is ready to transfer data is not required. This is accomplished by logic circuitry which expands a clock signal pulse which is applied to the microprocessor chip whenever a memory location is addressed which has a longer access time than is consistent with the width of the pulse ordinarily applied to the microprocessor to effect its operation.

대표청구항 ▼

A microprocessor system comprising: a clock signal source for producing a clock signal including a sequence of periodic clock pulses; data bus means for transferring data in said microprocessor system; microprocessor means responsive to said clock signal and coupled to said data bus means for execut

A microprocessor system comprising: a clock signal source for producing a clock signal including a sequence of periodic clock pulses; data bus means for transferring data in said microprocessor system; microprocessor means responsive to said clock signal and coupled to said data bus means for executing program instructions in said microprocessor system; memory means responsive to said clock signal coupled to said data bus means for storing digital information and for storing said program instructions, said memory means including at least one slow access location having associated therewith a slower access time than other locations of said memory means; said memory means having an address input for effecting addressing of said slow access location; said microprocessor means incuding address means coupled to said memory means to effect addressing of said memory means; said clock signal source including circuit means responsive to said address input for increasing the duration of only one of said pulses of said clock signal by a first predetermined amount of time when said slow access location means is addressed, said first predetermined amount of time being such that the elapsed time between the time at which said location of said memory means is addressed and the time at which the trailing edge of said one of said pulses occurs exceeds by a second predetermined amount of time the minimum access time of said location of said memory means.