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Electrical package for LSI devices and assembly process therefor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/04
출원번호 US-0534967 (1974-12-20)
발명자 / 주소
  • Honn
  • James J.
  • Stuby
  • Kenneth P.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Redmond, Jr., Joseph C.
인용정보 피인용 횟수 : 274  인용 특허 : 1

초록 ▼

An electrical package for Large Scale Integrated (LSI) devices includes a carrier having (a) thermal expansion similar to a semiconductor, (b) a standard array of terminal pins (100 or more) and (c) a circuit transposer that is (i) a semiconductor material, typically silicon and (ii) readily persona

대표청구항

대표청구항이 없습니다.

이 특허에 인용된 특허 (1)

  1. Davidson Lewis A. (Reston VA) Duffy Michael C. (Vienna VA) Erickson Alvard J. (Reston VA) Gunther-Mohr Gerard R. (Chappaqua NY) Williams Richard A. (Candor NY), Functional package for complex electronic systems with polymer-metal laminates and thermal transposer.
    상세보기

이 특허를 인용한 특허 (274)

  1. Liu, Yong; Liu, Yumin; Yang, Hua; Maldo, Tiburcio A.; Rios, Margie T., 3D smart power module.
    상세보기
  2. Oganesian, Vage; Mohammed, Ilyas; Mitchell, Craig; Haba, Belgacem; Savalia, Piyush, Active chip on carrier or laminated chip having microelectronic element embedded therein.
    상세보기
  3. Oganesian, Vage; Mohammed, Ilyas; Mitchell, Craig; Haba, Belgacem; Savalia, Piyush, Active chip on carrier or laminated chip having microelectronic element embedded therein.
    상세보기
  4. Oganesian, Vage; Mohammed, Ilyas; Mitchell, Craig; Haba, Belgacem; Savalia, Piyush, Active chip on carrier or laminated chip having microelectronic element embedded therein.
    상세보기
  5. Anthony Thomas R. (Schenectady NY), Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers.
    상세보기
  6. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Apparatus for attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux.
    상세보기
  7. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Apparatus for attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux.
    상세보기
  8. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Apparatus for attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux.
    상세보기
  9. Cobbley,Chad A.; Ball,Michael B.; Waddel,Marjorie L., Apparatus for locating conductive spheres utilizing screen and hopper of solder balls.
    상세보기
  10. Robinson, Marc E.; Vindasius, Alfons; Almen, Donald; Jacobsen, Larry, Assembly having stacked die mounted on substrate.
    상세보기
  11. Vindasius, Al; Robinson, Marc E.; Jacobsen, Larry; Almen, Donald, Assembly having stacked die mounted on substrate.
    상세보기
  12. Lin, Charles Wen Chyang, Bumpless flip chip assembly with solder via.
    상세보기
  13. Ahn, Kie Y.; Forbes, Leonard, Buried ground plane for high performance system modules.
    상세보기
  14. Cooney, Robert C.; Wilkinson, Joseph M., Circuit board with an attached die and intermediate interposer.
    상세보기
  15. Yoshizawa Tetsuo,JPX ; Nishida Hideyuki,JPX ; Imaizumi Masaaki,JPX ; Ichida Yasuteru,JPX ; Konishi Masaki,JPX ; Kondo Hiroshi,JPX ; Sakaki Takashi,JPX, Circuit member and electric circuit device with the connecting member.
    상세보기
  16. Werbizky George G. (Vestal NY), Circuit module with separate signal and power connectors.
    상세보기
  17. Uzoh, Cyprian Emeka, Compact semiconductor package and related methods.
    상세보기
  18. Uzoh, Cyprian Emeka, Compact semiconductor package and related methods.
    상세보기
  19. Uzoh, Cyprian Emeka, Compact semiconductor package and related methods.
    상세보기
  20. McDavid James M. (Dallas TX), Compact silicon module for high density integrated circuits.
    상세보기
  21. Hatano Hiromitsu,JPX ; Yashiro Akira,JPX, Complementary wiring package and method for mounting a semi-conductive IC package in a high-density board.
    상세보기
  22. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Savalia, Piyush; Mitchell, Craig, Compliant interconnects in wafers.
    상세보기
  23. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Savalia, Piyush; Mitchell, Craig, Compliant interconnects in wafers.
    상세보기
  24. Vindasius Alfons ; Robinson Marc E. ; Scharrenberg William R., Conductive epoxy flip-chip on chip.
    상세보기
  25. Jergovic, Ilija; Lacap, Efren M., Conductive routings in integrated circuits using under bump metallization.
    상세보기
  26. Jergovic, Ilija; Lacap, Efren M., Conductive routings in integrated circuits using under bump metallization.
    상세보기
  27. Jergovic, Ilija; Lacap, Efren M., Conductive routings in integrated circuits using under bump metallization.
    상세보기
  28. Yamasaki Kozo,JPX ; Saiki Hajime,JPX, Connecting board.
    상세보기
  29. Akram, Salman, Copper interconnect.
    상세보기
  30. Akram,Salman, Copper interconnect.
    상세보기
  31. Akram,Salman, Copper interconnect.
    상세보기
  32. Akram,Salman, Copper interconnect for semiconductor device.
    상세보기
  33. Prevost Michel (Le Plessis-Robinson FRX), Device for interconnection between and integrated circuit and an electrical circuit.
    상세보기
  34. Robinson, Marc E.; Vindasius, Alfons; Almen, Donald; Jacobsen, Larry, Die assembly having electrical interconnect.
    상세보기
  35. Lee,Teck Kheng; Lee,Kian Chai; Khoo,Sian Yong, Double bumping of flexible substrate for first and second level interconnects.
    상세보기
  36. Bickford Harry R. (57 Sherwood Ave. Ossining NY 10562) Bregman Mark F. (63 Old Washington Rd. Ridgefield CT 06877) Moskowitz Paul A. (R.D. #1 ; Box 343 ; Hunterbrook Rd. Yorktown Heights NY 10598) Pa, Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and pr.
    상세보기
  37. Dranchak David William ; Kelleher Robert Joseph ; Pagnani David Peter ; Zippetelli Patrick Robert, Dual substrate package assembly coupled to a conducting member.
    상세보기
  38. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
    상세보기
  39. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
    상세보기
  40. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
    상세보기
  41. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
    상세보기
  42. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking.
    상세보기
  43. Haba, Belgacem; Oganesian, Vage, Edge connect wafer level stacking with leads extending along edges.
    상세보기
  44. Dobritz, Stephan; Polaczyk, Christoph; Irsigler, Roland, Electric device, stack of electric devices, and method of manufacturing a stack of electric devices.
    상세보기
  45. DiStefano, Thomas H.; Fjelstad, Joseph, Electrical connection with inwardly deformable contacts.
    상세보기
  46. Distefano Thomas H. ; Fjelstad Joseph, Electrical connection with inwardly deformable contacts.
    상세보기
  47. Distefano, Thomas H.; Fjelstad, Joseph, Electrical connection with inwardly deformable contacts.
    상세보기
  48. DiStefano Thomas H. ; Smith John W. ; Karavakis Konstantine N. ; Kovac Zlata ; Fjelstad Joseph, Electrical connections with deformable contacts.
    상세보기
  49. DiStefano Thomas H. ; Smith John W. ; Karavakis Konstantine N. ; Kovac Zlata ; Fjelstad Joseph, Electrical connections with deformable contacts.
    상세보기
  50. David R. Hembree, Electrical connector.
    상세보기
  51. Knechtel, Roy; Dempwolf, Sophia; Guenther, Daniela; Schwarz, Uwe, Electrically conductive via(s) in a semiconductor substrate and associated production method.
    상세보기
  52. Cadet Yves,FRX ; Tutka Andre,FRX, Electronic card assembly by means of solder connections.
    상세보기
  53. Khandros, Igor Y.; Pedersen, David V.; Eldridge, Benjamin N.; Roy, Richard S.; Mathieu, Gaetan, Electronic component overlapping dice of unsingulated semiconductor wafer.
    상세보기
  54. Hauser, Christian; Reiss, Martin, Electronic component with a semiconductor chip, and method of producing the electronic component.
    상세보기
  55. Haimerl, Alfred; Hedler, Harry; Pohl, Jens, Electronic component with flexible contacting pads and method for producing the electronic component.
    상세보기
  56. Haimerl,Alfred; Hedler,Harry; Pohl,Jens, Electronic component with flexible contacting pads and method for producing the electronic component.
    상세보기
  57. Herzog Achim,DEX ; Spachmann Jurgen,DEX ; Wagner Uwe,DEX ; Raica Thomas,DEX, Electronic control apparatus.
    상세보기
  58. Jan, Jong Rong; Lu, Tsai Hua; Chiu, Sao Ling; Kung, Ling Chen, Electronic devices including offset conductive bumps.
    상세보기
  59. Gazdik Charles E. (Endicott NY) McBride Donald G. (Binghamton NY), Electronic package assembly method.
    상세보기
  60. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive layers comprising copper and having a thickness of at least 0.5 micrometers.
    상세보기
  61. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive shunt layers.
    상세보기
  62. Lee, Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.
    상세보기
  63. Lee, Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.
    상세보기
  64. Lee,Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.
    상세보기
  65. Lee,Teck Kheng, Elimination of RDL using tape base flip chip on flex for die stacking.
    상세보기
  66. Gan, Kah Wee; Huang, Yaohuang; Jin, Yonggang, Embedded wafer level package for 3D and package-on-package applications, and method of manufacture.
    상세보기
  67. Gan, Kah Wee; Huang, Yaohuang; Jin, Yonggang, Embedded wafer level package for 3D and package-on-package applications, and method of manufacture.
    상세보기
  68. Pasco Robert W. ; Reddy Srinivasa S. N. ; Vallabhaneni Rao V., Enhanced interconnection to ceramic substrates.
    상세보기
  69. Khandros Igor Y. ; Eldridge Benjamin N. ; Mathieu Gaetan L., Fabricating interconnects and tips using sacrificial substrates.
    상세보기
  70. Wojnarowski Robert John (Ballston Lake NY) Gorczyca Thomas Bert (Schenectady NY), Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers.
    상세보기
  71. Moon,Ow Chee; Koon,Eng Meow, Flexible ball grid array chip scale packages.
    상세보기
  72. Lee, Teck Kheng, Flip chip packaging using recessed interposer terminals.
    상세보기
  73. Lee,Teck Kheng, Flip chip packaging using recessed interposer terminals.
    상세보기
  74. Goh, Kim-Yong; Luan, Jing-En, Flip-chip fan-out wafer level package for package-on-package applications, and method of manufacture.
    상세보기
  75. McMahon John F., Flip-chip having electrical contact pads on the backside of the chip.
    상세보기
  76. Burstein Andrew J. ; Nickel Charles, Flip-chip switching regulator.
    상세보기
  77. Yu, Chen-Hua; Chang, Hung-Pin; Lin, Yung-Chi; Yu, Chia-Lin; Hung, Jui-Pin; Hwang, Chien Ling, Heat dissipation by through silicon plugs.
    상세보기
  78. Polese Frank J. ; Ocheretyansky Vladimir, Heat-dissipating package for microcircuit devices.
    상세보기
  79. Polese Frank J. ; Ocheretyansky Vladimir, Heat-dissipating package for microcircuit devices and process for manufacture.
    상세보기
  80. Chu George D. (Newark CA), High performance plastic encapsulated package for integrated circuit die.
    상세보기
  81. Kolesar ; Jr. Edward S. (Beavercreek OH), Hybrid wafer scale microcircuit integration.
    상세보기
  82. Kolesar ; Jr. Edward S. (Beavercreek OH), Hybrid wafer scale microcircuit integration.
    상세보기
  83. Kaskoun, Kenneth; Gu, Shiqun; Swinnen, Bart, IC interconnect.
    상세보기
  84. Zeber Kenneth Arthur (Oakland Park FL), Integrated circuit chip formed from processing two opposing surfaces of a wafer.
    상세보기
  85. Marcantonio Gabriel (Nepean CAX), Integrated circuit chip package.
    상세보기
  86. Marrs Robert C., Integrated circuit chip to substrate interconnection.
    상세보기
  87. Marrs Robert C., Integrated circuit chip to substrate interconnection and method.
    상세보기
  88. Gaul Stephen Joseph (Melbourne FL), Integrated circuit with edge connections and method.
    상세보기
  89. Mones Arthur H. (Raleigh NC) Sheehy Xavier (Park Ridge IL) Spielberger Richard K. (Maple Grove MN), Integrated semiconductor package.
    상세보기
  90. Blum Arnold (Gechingen DEX) Briska Marian (Rottenburg DEX) Najmann Knut (Gartringen DEX), Integrated wiring system for VLSI.
    상세보기
  91. Osaki Takaaki (Tokyo JPX) Matsui Norio (Tokyo JPX) Sasaki Shinichi (Iruma JPX) Egawa Yutaka (Tokyo JPX), Interboard connection terminal and method of manufacturing the same.
    상세보기
  92. Khandros Igor Y. ; Pedersen David V. ; Eldridge Benjamin N. ; Roy Richard S. ; Mathieu Gaetan, Interconnect assemblies and methods including ancillary electronic component connected in immediate proximity of semiconductor device.
    상세보기
  93. Bezuk Steve J. (Inver Grove Heights MN) Gheewala Tushar R. (Eagan MN) Campbell Stephen A. (Woodbury MN) Baseman Robert J. (Pleasantville NY), Interconnect for layered integrated circuit assembly.
    상세보기
  94. Khandros Igor Y. ; Mathieu Gaetan L., Interconnection substrates with resilient contact structures on both sides.
    상세보기
  95. Bohr, Mark T., Interposer and method of making same.
    상세보기
  96. Bohr,Mark T., Interposer and method of making same.
    상세보기
  97. Lee,Teck Kheng, Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods.
    상세보기
  98. Toh, Chin Hock; Huang, Yao Huang; Kolan, Ravi Kanth; Yuan, Wei Liang; Tanary, Susanto; Sun, Anthony Yi Sheng, Interposer for semiconductor package.
    상세보기
  99. Toh, Chin Hock; Huang, Yao Huang; Kolan, Ravi Kanth; Yuan, Wei Liang; Tanary, Susanto; Sun, Yi Sheng Anthony, Interposer for semiconductor package.
    상세보기
  100. Lee,Teck Kheng, Interposer substrate and wafer scale interposer substrate member for use with flip-chip configured semiconductor dice.
    상세보기
  101. Dozier, II, Thomas H.; Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Interposer, socket and assembly for socketing an electronic component and method of making and using same.
    상세보기
  102. Oganesian, Vage; Mohammed, Ilyas; Mitchell, Craig; Haba, Belgacem; Savalia, Piyush, Laminated chip having microelectronic element embedded therein.
    상세보기
  103. Degani Yinon ; Dudderar Thomas Dixon ; Frye Robert Charles, Low cost ball grid array package.
    상세보기
  104. McShane Michael B. (Austin TX), Low cost integrated circuit bonding process.
    상세보기
  105. Rinne,Glenn A.; Nair,Krishna K., Low temperature methods of bonding components and related structures.
    상세보기
  106. Farnworth Warren M., Mask repattern process.
    상세보기
  107. Farnworth Warren M., Mask repattern process.
    상세보기
  108. Farnworth Warren M., Mask repattern process.
    상세보기
  109. Farnworth Warren M., Mask repattern process.
    상세보기
  110. Farnworth, Warren M., Mask repattern process.
    상세보기
  111. Farnworth, Warren M., Mask repattern process.
    상세보기
  112. Warren M. Farnworth, Mask repattern process.
    상세보기
  113. Warren M. Farnworth, Mask repattern process.
    상세보기
  114. Ikeda, Hiroaki; Ishino, Masakazu, Memory module that is capable of controlling input/output in accordance with type of memory chip.
    상세보기
  115. Lee, Teck Kheng, Method and apparatus for dielectric filling of flip chip on interposer assembly.
    상세보기
  116. Akram, Salman, Method and semiconductor device having copper interconnect for bonding.
    상세보기
  117. Vindasius Alfons ; Robinson Marc E. ; Scharrenberg William R., Method for forming conductive epoxy flip-chip on chip.
    상세보기
  118. DiStefano, Thomas H.; Fjelstad, Joseph, Method for making a microelectronic interposer.
    상세보기
  119. Hirao Yasunobu (Toyokawa JPX) Koyama Makoto (Kariya JPX) Motoyama Yuji (Okazaki JPX), Method for producing multi-board electronic device.
    상세보기
  120. Hirao Yasunobu (Toyokawa JPX) Motoyama Yuji (Okazaki JPX) Nagasaka Takashi (Anjo JPX) Katsuyama Hidekazu (Nukata-gun JPX), Method for producing multi-board electronic device.
    상세보기
  121. Cooney, Robert C.; Wilkinson, Joseph M., Method of attaching die to circuit board with an intermediate interposer.
    상세보기
  122. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Method of attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux.
    상세보기
  123. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Method of attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux prior to placement.
    상세보기
  124. McAllister Michael Ford ; McDonald James Alexander ; Robbins Gordon Jay ; Swaminathan Madhavan ; Wilkins Gregory Martine, Method of constructing an integrated circuit memory.
    상세보기
  125. Fox Leslie R. (Boxborough MA) Wade Paul C. (Shirley MA) Schmidt William L. (Acton MA), Method of cooling and powering an integrated circuit chip using a compliant interposing pad.
    상세보기
  126. Geldermans Pieter (Poughkeepsie NY) Mathad Gangadhara S. (Poughkeepsie NY), Method of fabricating a chip interposer.
    상세보기
  127. Haba, Belgacem; Mohammed, Ilyas, Method of fabricating stacked assembly including plurality of stacked microelectronic elements.
    상세보기
  128. Haba, Belgacem, Method of fabricating stacked packages with bridging traces.
    상세보기
  129. Kaskoun, Kenneth; Gu, Shiqun; Swinnen, Bart, Method of fabricating via first plus via last IC interconnect.
    상세보기
  130. Gaul Stephen J. (Melbourne FL), Method of fabrication of surface mountable integrated circuits.
    상세보기
  131. Alfred Grill ; Jeffrey Curtis Hedrick ; Christopher Vincent Jahnes ; Satyanarayana Venkata Nitta ; Kevin S. Petrarca ; Sampath Purushothaman ; Katherine Lynn Saenger ; Stanley Joseph Whitehair, Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material.
    상세보기
  132. Farnworth, Warren M., Method of forming socket contacts.
    상세보기
  133. Farnworth,Warren M., Method of forming socket contacts.
    상세보기
  134. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.
    상세보기
  135. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.
    상세보기
  136. Akram,Salman, Method of improving copper interconnects of semiconductor devices for bonding.
    상세보기
  137. Cobbley Chad A. ; Ball Michael B. ; Waddel Marjorie L., Method of locating conductive spheres utilizing screen and hopper of solder balls.
    상세보기
  138. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., Method of locating conductive spheres utilizing screen and hopper of solder balls.
    상세보기
  139. Cobbley,Chad A.; Ball,Michael B.; Waddel,Marjorie L., Method of locating conductive spheres utilizing screen and hopper of solder balls.
    상세보기
  140. Haba, Belgacem; Oganesian, Vage, Method of making a stacked microelectronic package.
    상세보기
  141. Haba, Belgacem; Oganesian, Vage, Method of making a stacked microelectronic package.
    상세보기
  142. Bohr, Mark T., Method of making an interposer.
    상세보기
  143. Freyman Bruce J. (N. Lauderdale FL) Dorinski Dale (Coral Springs FL) Shurboff John (Coral Springs FL), Method of making an ultra high density pad array chip carrier.
    상세보기
  144. DiStefano Thomas H. (Monte Sereno CA) Smith John W. (Palo Alto CA) Karavakis Konstantine N. (Cupertino CA) Kovac Zlata (Los Gatos CA) Fjelstad Joseph (Sunnyvale CA), Method of making multilayer circuit.
    상세보기
  145. Yu, Chen-Hua; Chang, Hung-Pin; Lin, Yung-Chi; Yu, Chia-Lin; Hung, Jui-Pin; Hwang, Chien Ling, Method of manufacturing a semiconductor device including through silicon plugs.
    상세보기
  146. Yu, Chen-Hua; Chang, Hung-Pin; Lin, Yung-Chi; Yu, Chia-Lin; Hung, Jui-Pin; Hwang, Chien Ling, Method of manufacturing a semiconductor device including through silicon plugs.
    상세보기
  147. Osaka Takaaki (Tokyo JPX) Matsui Norio (Tokyo JPX) Susaki Shinichi (Iruma JPX) Egawa Yutaka (Tokyo JPX), Method of manufacturing an interboard connection terminal.
    상세보기
  148. Fox Leslie R. (Boxborough MA) Wade Paul C. (Shirley MA) Schmidt William L. (Acton MA), Method of packaging and powering integrated circuit chips and the chip assembly formed thereby.
    상세보기
  149. Hedler, Harry; Haimerl, Alfred, Method of producing an electronic component with flexible bonding.
    상세보기
  150. Lee, Teck Kheng, Methods for assembly and packaging of flip chip configured dice with interposer.
    상세보기
  151. Lee,Teck Kheng, Methods for assembly and packaging of flip chip configured dice with interposer.
    상세보기
  152. Lee,Teck Kheng, Methods for assembly and packaging of flip chip configured dice with interposer.
    상세보기
  153. Akram, Salman; Hembree, David R.; Farnworth, Warren M., Methods for electrical connector.
    상세보기
  154. Tuttle, Mark E., Methods for forming semiconductor device structures.
    상세보기
  155. Tuttle, Mark E., Methods for forming through-wafer interconnects and structures resulting therefrom.
    상세보기
  156. Werther William E. (Wood Ranch CA), Methods for interconnecting integrated circuits.
    상세보기
  157. Farnworth, Warren M., Methods for mask repattern process.
    상세보기
  158. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Methods of forming electronic structures including conductive shunt layers and related structures.
    상세보기
  159. Nair,Krishna K.; Rinne,Glenn A.; Batchelor,William E., Methods of forming electronic structures including conductive shunt layers and related structures.
    상세보기
  160. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Methods of forming lead free solder bumps.
    상세보기
  161. Rinne, Glenn A., Methods of forming metal layers using multi-layer lift-off patterns.
    상세보기
  162. Lee, Teck Kheng; Tan, Cher Khng Victor, Methods of forming semiconductor assemblies.
    상세보기
  163. Oganesian, Vage; Haba, Belgacem; Mitchell, Craig; Mohammed, Ilyas; Savalia, Piyush, Methods of forming semiconductor elements using micro-abrasive particle stream.
    상세보기
  164. Mis,J. Daniel, Methods of forming solder bumps on exposed metal pads.
    상세보기
  165. Rinne,Glenn A., Methods of providing solder structures for out plane connections.
    상세보기
  166. Dozier, II, Thomas H.; Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Methods of removably mounting electronic components to a circuit board, and sockets formed by the methods.
    상세보기
  167. Jan,Jong Rong; Lu,Tsai Hua; Chiu,Sao Ling; Kung,Ling Chen, Methods of selectively bumping integrated circuit substrates and related structures.
    상세보기
  168. Khandros,Igor Y.; DiStefano,Thomas H., Microelectronic component and assembly having leads with offset portions.
    상세보기
  169. Khandros,Igor Y.; DiStefano,Thomas H., Microelectronic component and assembly having leads with offset portions.
    상세보기
  170. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure.
    상세보기
  171. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure and method of making same.
    상세보기
  172. Lee,Teck Kheng, Microelectronic devices including underfill apertures.
    상세보기
  173. Oganesian, Vage; Mohammed, Ilyas; Mitchell, Craig; Haba, Belgacem; Savalia, Piyush, Microelectronic elements having metallic pads overlying vias.
    상세보기
  174. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Microelectronic elements with rear contacts connected with via first or via middle structures.
    상세보기
  175. Haba, Belgacem; Humpston, Giles, Microelectronic packages fabricated at the wafer level and methods therefor.
    상세보기
  176. Rinne Glenn A. ; Deane Philip A., Microelectronic packaging using arched solder columns.
    상세보기
  177. Rinne Glenn A. ; Deane Philip A., Microelectronic packaging using arched solder columns.
    상세보기
  178. Vindasius,Al; Robinson,Marc; Jacobsen,Larry; Almen,Donald, Micropede stacked die component assembly.
    상세보기
  179. Kaw Ravindhar K. (San Jose CA), Monolithic semiconductor chip interconnection technique and arrangement.
    상세보기
  180. Neugebauer Constantine A. (Schenectady NY) Levinson Lionel M. (Schenectady NY) Glascock ; II Homer H. (Scotia NY) Eichelberger Charles W. (Schenectady NY) Wojnarowski Robert J. (Ballston Lake NY) Car, Multi-chip interconnection package.
    상세보기
  181. Samaras William A. ; Phillips Paul T. ; Brownell Michael P., Multi-chip land grid array carrier.
    상세보기
  182. Samaras William A. ; Phillips Paul T. ; Brownell Michael P., Multi-chip land grid array carrier.
    상세보기
  183. Smolley Robert (Porteughese Bend CA), Multi-element circuit construction.
    상세보기
  184. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Multi-function and shielded 3D interconnects.
    상세보기
  185. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Multi-function and shielded 3D interconnects.
    상세보기
  186. Arnold Anthony F. (Poughkeepsie NY) Corso Joseph A. (Stormville NY) Kapur Shukla (Fishkill NY) Lange Walter F. (Longmont CO) Shih Da-Yuan (Poughkeepsie NY), Multilayer thin film metallurgy for pin brazing.
    상세보기
  187. Grill, Alfred; Hedrick, Jeffrey Curtis; Jahnes, Christopher Vincent; Nitta, Satyanarayana Venkata; Petrarca, Kevin S.; Purushothaman, Sampath; Saenger, Katherine Lynn; Whitehair, Stanley Joseph, Multilevel interconnect structure containing air gaps and method for making.
    상세보기
  188. Yu Allen S. ; Steffan Paul J. ; Scholer Thomas C., Multiple chip hybrid package using bump technology.
    상세보기
  189. Batchelor, William E.; Rinne, Glenn A., Non-Circular via holes for bumping pads and related structures.
    상세보기
  190. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip VIAS in stacked chips.
    상세보기
  191. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura, Off-chip vias in stacked chips.
    상세보기
  192. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip vias in stacked chips.
    상세보기
  193. Haba, Belgacem; Mohammed, Ilyas; Oganesian, Vage; Ovrutsky, David; Mirkarimi, Laura Wills, Off-chip vias in stacked chips.
    상세보기
  194. Rinne,Glenn A., Optical structures including liquid bumps and related methods.
    상세보기
  195. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Haba, Belgacem; Oganesian, Vage, Packaged semiconductor chips.
    상세보기
  196. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Oganesian, Vage, Packaged semiconductor chips with array.
    상세보기
  197. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Oganesian, Vage, Packaged semiconductor chips with array.
    상세보기
  198. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Oganesian, Vage, Packaged semiconductor chips with array.
    상세보기
  199. Grinman, Andrey; Ovrutsky, David; Rosenstein, Charles; Oganesian, Vage, Packaged semiconductor chips with array.
    상세보기
  200. Ng, Kwok K.; Sze, Simon M., Packaging microminiature devices.
    상세보기
  201. Wehnelt Ulrich (Soecking DEX), Printed circuit board for electronics.
    상세보기
  202. Zalesinski Jerzy M. (Essex Junction VT) Emerick Alan J. (Warren Center PA), Process for fabricating an electronic circuit package.
    상세보기
  203. Akram,Salman; Farnworth,Warren M., Process of forming socket contacts.
    상세보기
  204. Brown Candice H. (San Jose CA), Process of making a semiconductor device having parallel leads directly connected perpendicular to integrated circuit la.
    상세보기
  205. Haba, Belgacem; Humpston, Giles; Ovrutsky, David; Mirkarimi, Laura, Reconstituted wafer stack packaging with after-applied pad extensions.
    상세보기
  206. Haba, Belgacem; Humpston, Giles; Ovrutsky, David; Mirkarimi, Laura Wills, Reconstituted wafer stack packaging with after-applied pad extensions.
    상세보기
  207. Chang, Hung-Pin; Yu, Chen-Hua, Reduction of etch microloading for through silicon vias.
    상세보기
  208. Chang, Hung-Pin; Yu, Chen-Hua, Reduction of etch microloading for through silicon vias.
    상세보기
  209. Ashiya, Hiroyuki; Suzuki, Masataka; Tanaka, Yoshiyuki; Matsuura, Shingo, Relay device and relay device mounting structure.
    상세보기
  210. Pratt, David S., Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices.
    상세보기
  211. Pratt, David S., Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices.
    상세보기
  212. Lee, Jong-Joo, Semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack, a semiconductor device package and an electronic apparatus including the semiconductor chip.
    상세보기
  213. Fjelstad Joseph ; Karavakis Konstantine, Semiconductor chip package with fan-in leads.
    상세보기
  214. Lee, Min Hyung, Semiconductor chip, method of fabricating the same and semiconductor chip stack package.
    상세보기
  215. Iizuka Tetsuya (Funabashi JPX), Semiconductor device.
    상세보기
  216. Toshio Sugano (Kokubunji JPX) Seiichirou Tsukui (Komoro JPX) Shigeru Suzuki (Kokubunji JPX), Semiconductor device.
    상세보기
  217. Umemoto,Mitsuo; Tanida,Kazumasa, Semiconductor device and manufacturing method of the same.
    상세보기
  218. Lee, Teck Kheng, Semiconductor device assemblies.
    상세보기
  219. Akram, Salman, Semiconductor device having copper interconnect for bonding.
    상세보기
  220. Farnworth, Warren M.; Wood, Alan G., Semiconductor device including through-wafer interconnect structure.
    상세보기
  221. Tuttle, Mark E., Semiconductor device structures.
    상세보기
  222. Tuttle, Mark E., Semiconductor device structures and printed circuit boards comprising semiconductor devices.
    상세보기
  223. Lee,Teck Kheng; Tan,Cher Khng Victor, Semiconductor die packages with recessed interconnecting structures.
    상세보기
  224. Lee,Teck Kheng; Tan,Cher Khng Victor, Semiconductor die packages with recessed interconnecting structures and methods for assembling the same.
    상세보기
  225. Ishino, Masakazu; Ikeda, Hiroaki; Shibata, Kayoko, Semiconductor memory device and manufacturing method thereof.
    상세보기
  226. Ishino, Masakazu; Ikeda, Hiroaki; Shibata, Kayoko, Semiconductor memory device and manufacturing method thereof.
    상세보기
  227. Ishino, Masakazu; Ikeda, Hiroaki; Shibata, Kayoko, Semiconductor memory device and manufacturing method thereof.
    상세보기
  228. Ishino, Masakazu; Ikeda, Hiroaki; Shibata, Kayoko, Semiconductor memory device and manufacturing method thereof.
    상세보기
  229. Nam, Tae-Duk; Kim, Jin-Ho; Kim, Hyuk-Su; Kim, Hyoung-Suk; Lee, Tae-Young, Semiconductor package having supporting plate and method of forming the same.
    상세보기
  230. Nam, Tae-Duk; Kim, Jin-Ho; Kim, Hyuk-Su; Kim, Hyoung-Suk; Lee, Tae-Young, Semiconductor package having supporting plate and method of forming the same.
    상세보기
  231. Jin, Yonggang, Semiconductor package with improved pillar bump process and structure.
    상세보기
  232. Haba, Belgacem; Humpston, Giles; Margalit, Moti, Semiconductor packaging process using through silicon vias.
    상세보기
  233. Clements Ken (Santa Cruz CA), Semiconductor wafer array.
    상세보기
  234. Fukushima Toshitaka (Yokohama JPX), Semiconductor wafer-scale integrated device composed of interconnected multiple chips each having an integration circuit.
    상세보기
  235. Magerlein, John H.; Patel, Chirag S.; Sprogis, Edmund J.; Stoller, Herbert I., Silicon based package.
    상세보기
  236. MacNamara, Cormac; Brogan, Conor; Griffin, Hiugh J.; Wilson, Robin, Silicon wafer having through-wafer vias.
    상세보기
  237. MacNamara, Cormac; Brogan, Conor; Griffin, Hugh J.; Wilson, Robin, Silicon wafer having through-wafer vias.
    상세보기
  238. Dozier, II, Thomas H.; Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L.; Pederson, David V.; Stadt, Michael A., Sockets for "springed" semiconductor devices.
    상세보기
  239. Dozier, II,Thomas H.; Eldridge,Benjamin N.; Grube,Gary W.; Khandros,Igor Y.; Mathieu,Gaetan L.; Pedersen,David V.; Stadt,Michael A., Sockets for "springed" semiconductor devices.
    상세보기
  240. Danner Paul A. (Beaverton OR), Solder ball array and method of preparation.
    상세보기
  241. Dozier ; II Thomas H. ; Khandros Igor Y., Solder preforms.
    상세보기
  242. Rinne, Glenn A., Solder structures for out of plane connections.
    상세보기
  243. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Solder structures including barrier layers with nickel and/or copper.
    상세보기
  244. Werther William E., Space-saving assemblies for connecting integrated circuits to circuit boards.
    상세보기
  245. Avsian, Osher; Grinman, Andrey; Humpston, Giles; Margalit, Moti, Stack packages using reconstituted wafers.
    상세보기
  246. Haba, Belgacem; Mohammed, Ilyas, Stacked assembly including plurality of stacked microelectronic elements.
    상세보기
  247. Igor Y. Khandros ; Thomas H. DiStefano, Stacked chip assembly.
    상세보기
  248. Vindasius,Al; Robinson,Marc; Jacobsen,Larry; Almen,Donald, Stacked die BGA or LGA component assembly.
    상세보기
  249. Rinne,Glenn A., Stacked electronic structures including offset substrates.
    상세보기
  250. Kriman, Moshe; Avsian, Osher; Haba, Belgacem; Humpston, Giles; Burshtyn, Dmitri, Stacked microelectronic assemblies having vias extending through bond pads.
    상세보기
  251. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVS formed in stages and carrier above chip.
    상세보기
  252. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVS formed in stages and carrier above chip.
    상세보기
  253. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVS formed in stages with plural active chips.
    상세보기
  254. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVs formed in stages with plural active chips.
    상세보기
  255. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Stacked microelectronic assembly with TSVs formed in stages with plural active chips.
    상세보기
  256. Ikeda, Masato, Stacked package and method for forming stacked package.
    상세보기
  257. Nguyen, Chinh; Hoang, Phu; Hoang, Phan; Le, Andy, Stacking multiple devices using direct soldering.
    상세보기
  258. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Staged via formation from both sides of chip.
    상세보기
  259. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Staged via formation from both sides of chip.
    상세보기
  260. Oganesian, Vage; Haba, Belgacem; Mohammed, Ilyas; Mitchell, Craig; Savalia, Piyush, Staged via formation from both sides of chip.
    상세보기
  261. Marks Robert (South Burlington VT) Phelps ; Jr. Douglas W. (Burlington VT) Ward William C. (Burlington VT), Substrate with multiple type connections.
    상세보기
  262. Gaul Stephen J. (Melbourne FL), Surface mountable integrated circuit with conductive vias.
    상세보기
  263. Jones Robert E. (Saint Peters MO), Surface mounted component adaptor for interconnecting of surface mounted circuit components.
    상세보기
  264. Cobbley, Chad A.; Ball, Michael B.; Waddel, Marjorie L., System for locating conductive sphere utilizing screen and hopper of solder balls.
    상세보기
  265. Cobbley,Chad A.; Ball,Michael B.; Waddel,Marjorie L., System for locating conductive sphere utilizing screen and hopper of solder balls.
    상세보기
  266. Young Peter L. (South Barrington IL) Cech Jay (Elmhurst IL) Li Kin (Lombard IL), Thin-film electrical connections for integrated circuits.
    상세보기
  267. Vindasius, Al; Robinson, Marc, Three dimensional six surface conformal die coating.
    상세보기
  268. Kato Takashi (Sagamihara JPX) Taguchi Masao (Sagamihara JPX), Three-dimensional integrated circuit and manufacturing method thereof.
    상세보기
  269. Andrew J. Burstein ; Charles Nickel, Transistor pattern for voltage regulator.
    상세보기
  270. Myers,Todd B; Watts,Nicholas R.; Palmer,Eric C; Defeo,Renee M; Lim,Jui Min, Via including multiple electrical paths.
    상세보기
  271. Stopper Herbert (Orchard Lake MI) Perkins Cornelius C. (Brimingham MI), Wafer and method of making same.
    상세보기
  272. Haba, Belgacem; Mohammed, Ilyas; Mirkarimi, Laura; Kriman, Moshe, Wafer level edge stacking.
    상세보기
  273. Stopper Herbert (Orchard Lake MI) Perkins Cornelius C. (Birmingham MI), Wafer scale package system and header and method of manufacture thereof.
    상세보기
  274. Sakaguchi, Hideaki; Murayama, Kei, Wiring board having heat intercepting member.
    상세보기

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