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MNOS non-volatile memory with write cycle suppression 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-007/00
  • G11C-011/40
출원번호 US-0755280 (1976-12-29)
발명자 / 주소
  • Cricchi
  • James R.
출원인 / 주소
  • Westinghouse Electric Corp.
대리인 / 주소
    Trepp, R. M.
인용정보 피인용 횟수 : 57  인용 특허 : 1

초록

An improved memory for storing digital data is described incorporating two variable threshold transistors per memory cell which are written in opposite directions concomitantly by applying a polarizing voltage across the gate insulator of each transistor. Subsequent writing into the memory cell is l

대표청구항

대표청구항이 없습니다.

이 특허에 인용된 특허 (1)

  1. Horninger Karlheinrich (Eglharting DT), Associative storage circuit.

이 특허를 인용한 특허 (57)

  1. Hori Chikahiro (Kanagawa JPX), Associative memory device including write inhibit circuitry.
  2. Fang Sheng (E. Palo Alto CA) Rao Kameswara K. (Santa Clara CA), Byte wide EEPROM with individual write circuits.
  3. Fang Sheng (Sunnyvale CA), Byte wide EEPROM with individual write circuits and write prevention means.
  4. Lonky Martin L. (Baltimore MD), Drain triggered N-channel non-volatile memory.
  5. Banks Gerald J., Electrically alterable non-violatile memory with N-bits per cell.
  6. Fitzpatrick Michael D. (Linthicum MD), Electrically alterable non-volatile memory.
  7. Gerald J. Banks, Electrically alterable non-volatile memory with N-Bits per cell.
  8. Banks Gerald J., Electrically alterable non-volatile memory with N-bits per cell.
  9. Banks, Gerald J., Electrically alterable non-volatile memory with N-bits per cell.
  10. Banks Gerald J., Electrically alterable non-volatile memory with n-bits per cell.
  11. Banks Gerald J., Electrically alterable non-volatile memory with n-bits per cell.
  12. Banks Gerald J., Electrically alterable non-volatile memory with n-bits per cell.
  13. Banks, Gerald J., Electrically alterable non-volatile memory with n-bits per cell.
  14. Banks, Gerald J., Electrically alterable non-volatile memory with n-bits per cell.
  15. Banks,Gerald J., Electrically alterable non-volatile memory with n-bits per cell.
  16. Gerald J. Banks, Electrically alterable non-volatile memory with n-bits per cell.
  17. Gerald J. Banks, Electrically alterable non-volatile memory with n-bits per cell.
  18. Gerald J. Banks, Electrically alterable non-volatile memory with n-bits per cell.
  19. Gerald J. Banks, Electrically alterable non-volatile memory with n-bits per cell.
  20. Harari Eliyahou ; Norman Robert D. ; Mehrotra Sanjay, Flash EEPROM system.
  21. Eliyahou Harari ; Robert D. Norman ; Sanjay Mehrotra, Flash EEprom system.
  22. Eliyahou Harari ; Sanjay Mehrotra, Flash EEprom system.
  23. Harari Eliyahou ; Mehrotra Sanjay, Flash EEprom system.
  24. Harari, Eliyahou; Norman, Robert D.; Mehrotra, Sanjay, Flash EEprom system.
  25. Harari,Eliyahou; Norman,Robert D.; Mehrotra,Sanjay, Flash EEprom system.
  26. Harari,Eliyahou; Norman,Robert D.; Mehrotra,Sanjay, Flash EEprom system.
  27. Harari,Eliyahou; Norman,Robert D.; Mehrotra,Sanjay, Flash EEprom system capable of selective erasing and parallel programming/verifying memory cell blocks.
  28. Harari Eliyahou ; Norman Robert D. ; Mehrotra Sanjay, Flash EEprom system with cell by cell programming verification.
  29. Eliyahou Harari, Highly compact EPROM and flash EEPROM devices.
  30. Pesavento, Alberto, Hybrid non-volatile memory.
  31. Vermesse Bernard (L\Hay les Roses FRX), Limited write non-volatile memory and a franking machine making use thereof.
  32. Adam Fritz G. (Freiburg DEX), Low power push-pull CMOS driver circuit.
  33. Hedin Raymond C. (Apple Valley MN) Amundson Dennis L. (Bloomington MN), MNOS Over-write protection circuitry.
  34. Banks Gerald J., Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell.
  35. Banks Gerald J., Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell.
  36. Banks, Gerald J., Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell.
  37. Banks, Gerald J., Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell.
  38. Banks,Gerald J., Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell.
  39. Banks,Gerald J., Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell.
  40. Banks,Gerald J., Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell.
  41. Gerald J. Banks, Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell.
  42. Gerald J. Banks, Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell.
  43. Harari,Eliyahou; Norman,Robert D.; Mehrotra,Sanjay, Method for selective erasing and parallel programming/verifying of cell blocks in a flash EEprom system.
  44. Garde Douglas (Dover MA), Multi-port register file with flow-through of data.
  45. Bernstein, Kerry, Multi-port register implementations.
  46. Furman Anatol (Jericho VT), Multi-port register implementations.
  47. Bernstein Kerry (South Burlington VT), Multi-port system.
  48. Harari Eliyahou ; Norman Robert D. ; Mehrotra Sanjay, Multi-state flash EEprom system with selective multi-sector erase.
  49. Nitta, Fumihiko; Kobayashi, Shinichi, Nonvolatile semiconductor memory device.
  50. Fang Sheng (E. Palo Alto CA) Rao Kameswara K. (Santa Clara CA), One step write circuit arrangement for EEPROMS.
  51. Maeda Kohichi (Yokohama JPX) Yoshida Masanobu (Kawaguchi JPX), Semiconductor device.
  52. Kawai, Koichi; Imamiya, Kenichi, Semiconductor memory device and test method thereof.
  53. Kawai,Koichi; Imamiya,Kenichi, Semiconductor memory device and test method thereof.
  54. Oehler Harry G. (Pasadena MD), Sense circuit for use in variable threshold transistor memory arrays.
  55. Bernstein Kerry (South Burlington VT), Support circuitry for multi-port systems.
  56. Pesavento, Alberto, pFET nonvolatile memory.
  57. Pesavento, Alberto; Hyde, John D., pFET nonvolatile memory.
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