이 특허를 인용한 특허 (21)

1. Farnworth, Warren M., Energy beam patterning of protective layers for semiconductor devices.

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2. Clecak Nicholas J. (San Jose CA) Grant Barbara D. (San Jose CA) Willson Carlton G. (San Jose CA), Lithographic resist composition for a lift-off process.

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3. Christopher David McCullough ; Kevin Barry Ray GB; Alan Stanley Monk GB; John David Riches GB; Anthony Paul Kitson GB; Gareth Rhodri Parsons GB; David Stephen Riley GB, Manufacture of lithographic printing forms.

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4. Dunkleberger La Rue N. (High Bridge NJ), Mask structure for depositing patterned thin films.

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5. Kato Yoshihide (Kawasaki JPX) Kirita Kei (Tokyo JPX) Shinozaki Toshiaki (Yokohama JPX) Shigemitsu Fumiaki (Yokohama JPX) Usuda Kinya (Yokohama JPX) Tsuchiya Takashi (Urawa JPX), Method and apparatus for forming resist pattern.

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6. Leedy, Glenn, Method and system for probing, testing, burn-in, repairing and programming of integrated circuits in a closed environment using a single apparatus.

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7. Bobbio Stephen M. (Wake Forest NC), Method for anisotropically hardening a protective coating for integrated circuit manufacture.

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8. Krog, Jens Peter; Eriksen, Gert Friis; Dyrbye, Karsten, Method for producing electronic components and pressure sensor.

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9. Matsuzawa, Toshiharu; Douta, Kikuo; Iwayanagi, Takao; Yanazawa, Hiroshi, Method of forming a microscopic pattern.

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10. Shigemitsu Fumiaki (Yokohama JPX) Usuda Kinya (Yokohama JPX) Nomaki Tatsuo (Yokohama JPX), Method of forming resist pattern.

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11. McCullough, Christopher David; Ray, Kevin Barry; Monk, Alan Stanley Victor; Riches, John David; Kitson, Anthony Paul; Parsons, Gareth Rhodri; Riley, David Stephen; Bennett, Peter Andrew Reath; Hoare,, Method of making masks and electronic parts.

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12. Daniel Peter J. (Dorking GB2), Method of manufacturing solid-state devices in which planar dimensional distortion is reduced.

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13. Leedy Glenn J. (Santa Barbara CA), Method of repairing an integrated circuit structure.

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14. Leedy Glenn J., Method of repairing defective traces in an integrated circuit structure.

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15. Sakaguchi, Kenji; Fuyutsume, Toshiyuki; Koshido, Yoshihiro, Methods of forming resist pattern, forming electrode pattern, and manufacturing surface acoustic wave device.

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16. Badami Dinesh A. (Williston VT) Hakey Mark C. (Milton VT) Moritz Holger (Holzgerlingen DEX), Process for delineating photoresist lines at pattern edges only using image reversal composition with diazoquinone.

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17. Nesbitt Raymond A. (Henrico County VA), Process for improved wall definition of an additive printed circuit.

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18. Trausch Gnter E. (Munich DEX), Process for the manufacture of precision templates.

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19. Dev, Alok, Silicon carbide schottky barrier diode and method of making.

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20. Leedy, Glenn, System for probing, testing, burn-in, repairing and programming of integrated circuits.

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21. Liu Shing-Gong (Princeton NJ) Duigon Ferdinand C. (East Brunswick NJ), Thin film pattern generation by an inverse self-lifting technique.

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