이 특허를 인용한 특허 (207)

1. Van Hook, Timothy J.; Hsu, Peter Yan-Tek; Huffman, William A.; Moreton, Henry P.; Killian, Earl A., Alignment and ordering of vector elements for single instruction multiple data processing.

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2. van Hook Timothy J. ; Hsu Perter ; Huffman William A. ; Moreton Henry P. ; Killian Earl A., Alignment and ordering of vector elements for single instruction multiple data processing.

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3. van Hook,Timothy J.; Hsu,Peter; Huffman,William A.; Moreton,Henry P.; Killian,Earl A., Alignment and ordering of vector elements for single instruction multiple data processing.

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4. Kort Raymond C. (New Brighton MN) Kelley James W. (Stacy MN), Apparatus for converting serial input sparse vector format to parallel unpacked format for input to tandem arithmetic lo.

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5. Wassel Edward R. (Endwell NY) Watkins Gerald J. (Endicott NY), Apparatus for executing an instruction and for simultaneously generating and storing related information.

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6. Wang, Yulun; Uecker, Darrin R.; Laby, Keith Phillip; Wilson, Jeff; Jordan, Steve; Wright, James, Apparatus for performing minimally invasive cardiac procedures with a robotic arm that has a passive joint and system which can decouple the robotic arm from the input device.

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7. Schiffleger Alan J. (Chippewa Falls WI), Apparatus for sharing memory in a multiprocessor system.

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8. Babaian Boris A.,RUX ; Gorokhov Valeri G.,RUX ; Gruzdov Feodor A.,RUX ; Sakhin Yuli Kh.,RUX ; Volkonski Vladimir Yu.,RUX, Array prefetch apparatus and method.

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9. Works George A. (San Diego CA) Hicks William L. (San Diego CA) Kasbo Richard L. (San Diego CA) Muenchau Ernest E. (San Diego CA) Deiss Stephen R. (Encinitas CA), Array processor.

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10. Wang, Yulun; Laby, Keith P.; Uecker, Darrin R.; Mangaser, Amante A.; Ghodoussi, Modjtaba, Automated endoscope system for optimal positioning.

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11. Uchida Keiichiro (Yokohama JPX) Tamura Hiroshi (Kawasaki JPX) Okamoto Tetsuro (Machida JPX) Okutani Shigeaki (Yokohama JPX), Bank interleaved vector processor having a fixed relationship between start timing signals.

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12. Ekner, Hartvig W. J.; Stribaek, Morten; Laursen, Soeren R. F., Binary polynomial multiplier.

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13. Matsuyama Shigeru (Tokyo JPX), Calculator for cross summing a plurality of operands.

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14. Childers Jim (Fort Bend TX) Reinecke Peter (Lockhart TX) Takahashi Yutaka (Ushiku JPX) Yamamoto Seiichi (Ibaragi JPX), Circuitry and method for performing two operating instructions during a single clock in a processing device.

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15. Wallach, Steven J.; Brewer, Tony, Compiler for generating an executable comprising instructions for a plurality of different instruction sets.

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16. Hamanaka Naoki (Tokyo JPX) Tanaka Teruo (Tokyo JPX) Omoda Koichiro (Kanagawa JPX) Nagashima Shigeo (Tokyo JPX) Nakagoshi Junji (Tokyo JPX) Ojima Kazuo (Tokyo JPX), Computer for synchronized read and write of vector data.

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17. Leedom George W ; Moore William T., Computer having multiple address ports, each having logical address translation with base and limit memory management.

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18. Wallach Steven J. (7314 Westerway Dallas TX 75248) Jones Thomas M. (6050 Glen Heather Dallas TX 75252) Marshall Frank J. (2316 Crossbend Rd. Plano TX 75023) Nobles David A. (3514 Corona Garland TX 75, Computer system.

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19. Izumisawa Hiroyuki (Tokyo JPX) Kinoshita Seiichiro (Tokyo JPX), Computer system for directly transferring vactor elements from register to register using a single instruction.

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20. Chen Steve S. (Chippewa Falls WI) Schiffleger Alan J. (Chippewa Falls WI) Somdahl Eugene R. (St. Paul MN) Higbie Lee (Arlington Heights IL), Computer vector multiprocessing control.

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21. Chen Steve S. (Chippewa Falls WI) Schiffleger Alan J. (Chippewa Falls WI), Computer vector multiprocessing control with multiple access memory and priority conflict resolution method.

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22. Dozier Harold W. (Carrollton TX) Jones Thomas M. (Dallas TX) Wallach Steven J. (Dallas TX) Gruger Jeffrey H. (Dallas TX), Concurrent processing of data operands.

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23. Moyer,William C., Conditional next portion transferring of data stream to or from register based on subsequent instruction aspect.

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24. Hamada,Mana; Kuromaru,Shunichi; Yonezawa,Tomonori; Nakamura,Tsuyoshi, Conditional vector arithmetic method and conditional vector arithmetic unit.

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25. Bhandarkar Dileep P. (Shrewsbury MA) Cutler Dave (Bellevue WA) Cardoza Wayne (Merrimack NH) Witek Rich (Littleton MA) Orbits Dave (Redmond WA), Context switching method and apparatus for use in a vector processing system.

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26. Moll, Frederic H.; Rosa, David J.; Ramans, Andris D.; Blumenkranz, Steven J.; Guthart, Gary S.; Niemeyer, Gunter D.; Nowlin, William C.; Salisbury, Jr., J. Kenneth; Tierney, Michael J., Cooperative minimally invasive telesurgical system.

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27. Moll, Frederic H.; Rosa, David J.; Ramans, Andris D.; Blumenkranz, Steven J.; Guthart, Gary S.; Niemeyer, Gunter D.; Nowlin, William C.; Salisbury, Jr., J. Kenneth; Tierney, Michael J., Cooperative minimally invasive telesurgical system.

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28. Moll, Frederic H.; Rosa, David J.; Ramans, Andris D.; Blumenkranz, Steven J.; Guthart, Gary S.; Niemeyer, Gunter D.; Nowlin, William C.; Salisbury, Jr., J. Kenneth; Tierney, Michael J., Cooperative minimally invasive telesurgical system.

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29. Moll, Frederic H.; Rosa, David J.; Ramans, Andris D.; Blumenkranz, Steven J.; Guthart, Gary S.; Niemeyer, Gunter D.; Nowlin, William C.; Salisbury, Jr., J. Kenneth; Tierney, Michael J., Cooperative minimally invasive telesurgical system.

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30. Torii Shunichi (Musashino JPX) Nagashima Shigeo (Hachioji JPX) Omoda Koichiro (Sagamihara JPX), Data processing apparatus.

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31. Hasegawa Kenji (Tokyo JPX), Data processing circuit for calculating either a total sum or a total product of a series of data at a high speed.

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32. Beard Douglas R. ; Phelps Andrew E. ; Woodmansee Michael A. ; Blewett Richard G. ; Lohman Jeffrey A. ; Silbey Alexander A. ; Spix George A. ; Simmons Frederick J. ; Van Dyke Don A., Data processing system for processing one and two parcel instructions.

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33. Tanakura Yoshiyuki (Numazu JPX) Uchida Keiichiro (Kawasaki JPX), Data processing system having a high speed pipeline processing architecture.

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34. Moyer,William C., Data processing system having instruction specifiers for SIMD register operands and method thereof.

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35. Nagashima, Shigeo; Torii, Shunichi; Omoda, Koichiro; Inagami, Yasuhiro, Data processing system including scalar data processor and vector data processor.

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36. Moyer, William C., Data processing system using independent memory and register operand size specifiers and method thereof.

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37. Moyer,William C.; Norris,James M.; May,Philip E.; Moat,Kent Donald; Essick, IV,Raymond B.; Lucas,Brian Geoffrey, Data processing system using multiple addressing modes for SIMD operations and method thereof.

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38. Torii Shunichi (Musashino JPX) Kojima Keiji (Kokubunji JPX) Ido Noriyasu (Yokohama JPX), Data processor with associative memory storing vector elements for vector conversion.

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39. Torii Shunichi (3-18 ; Gotenyama-2-chome Musashino-shi JPX) Nagashima Shigeo (40-27 ; Koyasumachi-1-chome Hachioji-shi JPX) Omoda Koichiro (1140 Tokawa ; Hadano-shi JPX), Data storage device.

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40. Kishi Tetsuji (Osaka JPX) Okabayashi Ichiro (Osaka JPX) Mori Yasuhiro (Osaka JPX) Migita Manabu (Osaka JPX) Kuwata Yuri (Hyogo JPX), Data transfer device and multiprocessor system.

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41. May,Philip E.; Lucas,Brian G.; Moat,Kent D., Dataflow graph compression for power reduction in a vector processor.

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42. Smith James E., Density dependent vector mask operation control apparatus and method.

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43. Kinoshita Kouji (Tokyo JPX), Device for controlling access to a computer memory.

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44. Nunamaker, Nathan Samuel; Randolph, Jack Chris; Tsuchiya, Kenichi, Digital data processing apparatus having multi-level register file.

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45. Nunamaker,Nathan Samuel; Randolph,Jack Chris; Tsuchiya,Kenichi, Digital data processing apparatus having multi-level register file.

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46. Wallach, Steven J.; Brewer, Tony, Dispatch mechanism for dispatching instructions from a host processor to a co-processor.

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47. Brewer, Tony; Wallach, Steven J., Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor.

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48. Robert Sidney Blackmore ; Xin Chen ; Rama Krishna Govindaraju ; Anan Vishwanath Hudli, Efficient non-contiguous I/O vector and strided data transfer in one sided communication on multiprocessor computers.

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49. Julian, Christopher A.; Ikeda, Michael; Ramans, Andris D.; Hoornaert, Dean F.; Isaac, Margaret M., Endoscopic beating-heart stabilizer and vessel occlusion fastener.

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50. Bhandarkar Dileep P. (Shrewsbury MA) Supnik Robert (Carlisle MA) Hobbs Steven (Westford MA), Exception reporting mechanism for a vector processor.

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51. Hartson,Ted E.; Dickinson,Robert V. C.; Ciciora,Walter S., Expanded information capacity for existing communication transmission systems.

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52. Stribaek, Morten; Paillier, Pascal, Extended precision accumulator.

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53. Stribaek,Morten; Paillier,Pascal, Extended precision accumulator.

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54. Stribaek,Morten; Paillier,Pascal, Extended-precision accumulation of multiplier output.

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55. Morris S. Brent (Columbia MD) Wisniewski Richard A. (West Friendship MD), Fast parallel sorting processor.

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56. Chen Steve S. (Chippewa Falls WI) Schiffleger Alan J. (Chippewa Falls WI), Flexible chaining in vector processor with selective use of vector registers as operand and result registers.

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57. Wang, Yulun; Jordan, Charles S.; Uecker, Darrin R.; Wooters, Charles C., General purpose distributed operating room control system.

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58. Wang,Yulun; Jordan,Charles S.; Uecker,Darrin R.; Wooters,Charles C., General purpose distributed operating room control system.

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59. Wang,Yulun; Jordan,Charles S.; Uecker,Darrin R.; Wooters,Charles C., General purpose distributed operating room control system.

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60. Wright, James; Wasti, Hamid; Uecker, Darrin R., Head cursor control interface for an automated endoscope system for optimal positioning.

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61. Snow,Edward Ramsey, Heart stabilizer.

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62. Wallach Steven J. (Dallas TX) Chastain David M. (Plano TX) Weatherford James R. (Lake Dallas TX), Hierarchical memory system with logical cache, physical cache, and address translation unit for generating a sequence of.

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63. Ngai Chuck H. (Endwell NY) Watkins Gerald J. (Endicott NY), High performance parallel vector processor having a modified vector register/element processor configuration.

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64. Pfeiffer David M. (Plano TX) Stoner David T. (McKinney TX) Norsworthy John P. (Carrollton TX) Dipert Dwight D. (Richardson TX) Thompson Jay A. (Plano TX) Fontaine James A. (Plano TX) Corry Michael K., High speed image processing system using separate data processor and address generator.

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65. Nguyen, Le Trong; Lentz, Derek J.; Miyayama, Yoshiyuki; Garg, Sanjiv; Hagiwara, Yasuaki; Wang, Johannes; Lau, Te Li; Wang, Sze Shun; Trang, Quang H., High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution.

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66. Nguyen,Le Trong; Lentz,Derek J.; Miyayama,Yoshiyuki; Garg,Sanjiv; Hagiwara,Yasuaki; Wang,Johannes; Lau,Te Li; Wang,Sze Shun; Trang,Quang H., High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution.

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67. Yano Haruo (Tokyo JPX), Information processing system comprising a register renewal waiting control circuit with renewal register number registe.

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68. Hicks Troy Neal ; Le Hung Qui ; Muhich John Stephen ; White Steven Wayne, Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-un.

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69. Torng Hwa C. (Ithaca NY), Instruction issuing mechanism for processors with multiple functional units.

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70. Harris Michael C. (Bedford TX) Chastain David M. (Plano TX) Gostin Gary B. (Coppell TX), Instruction processing unit for computer.

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71. Wright, James; Deacon, Jim; Westra, Hendrik S., Instrument guide.

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72. Chung, Wonzoo; Endres, Thomas J.; Long, Christopher D., Joint adaptive optimization of soft decision device and feedback equalizer.

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73. Chung,Wonzoo; Endres,Thomas J.; Long,Christopher D., Joint adaptive optimization of soft decision device and feedback equalizer.

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74. Endres, Thomas J.; Long, Christopher D.; Chung, Wonzoo; Fagan, Rory, Joint, adaptive control of equalization, synchronization, and gain in a digital communications receiver.

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75. Endres, Thomas J.; Long, Christopher D.; Chung, Wonzoo; Fagan, Rory, Joint, adaptive control of equalization, synchronization, and gain in a digital communications receiver.

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76. Cook Erick M. (San Diego CA) Phelps Andrew E. (San Diego CA) Potash Hanan (La Jolla CA), Linking scalar results directly to scalar operation inputs on a bidirectional databus in a computer which superpositions.

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77. Hamstra James R. (Plymouth MN) Koehler Howard A. (Minneapolis MN) Rusterholz John T. (Roseville MN) Tanglin David J. (Anoka MN), Local store for scientific vector processor.

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78. Rusterholz John T. (Roseville MN) Hamstra James R. (Plymouth MN), Loop control mechanism for scientific processor.

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79. Pomerene James H. (Chappaqua NY), Machine for multiple instruction execution.

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80. Renner, Karl; Shanklin, John P., Master/slave sequencing processor.

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81. Sazegari, Ali, Matrix multiplication in a vector processing system.

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82. Sazegari,Ali, Matrix multiplication in a vector processing system.

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83. Wang,Yulun; Uecker,Darrin; Laby,Keith P.; Wilson,Jeff D.; Jordan,Charles S.; Wright,James W.; Ghodoussi,Modjtaba, Medical robotic arm that is attached to an operating table.

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84. Wang, Yulun; Uecker, Darrin; Laby, Keith P.; Wilson, Jeff D.; Jordan, Charles S.; Wright, James W.; Ghodoussi, Modjtaba, Medical robotic system with different scaling factors.

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85. Brewer, Tony M.; Magee, Terrell; Andrewartha, J. Michael, Memory interleave for heterogeneous computing.

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86. Brewer, Tony M.; Magee, Terrell; Andrewartha, J. Michael, Memory interleave for heterogeneous computing.

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87. Wang,Gang; Hahn,Joseph F.; Mangaser,Amante; Roe,David B.; Steiner,Charles P.; Uecker,Darrin R., Method and apparatus for accessing medical data over a network.

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88. Norris,James M.; May,Philip E.; Moat,Kent D.; Essick, IV,Raymond B.; Lucas,Brian G., Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values.

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89. Beard Douglas R. (Eleva WI) Phelps Andrew E. (Eau Claire WI) Woodmansee Michael A. (Eau Claire WI) Blewett Richard G. (Altoona WI) Lohman Jeffrey A. (Eau Claire WI) Silbey Alexander A. (Eau Claire WI, Method and apparatus for chaining vector instructions.

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90. Liao, Yu Chung C.; Sandon, Peter A.; Cheng, Howard, Method and apparatus for efficient loading and storing of vectors.

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91. May,Philip E.; Essick, IV,Raymond B.; Lucas,Brian G.; Moat,Kent D.; Norris,James M., Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters.

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92. Bhandarkar Dileep P. (Shrewsbury MA) Supnik Robert (Carlisle MA) Fossum Tryggve (Northboro MA) Manley Dwight (Holliston MA), Method and apparatus for executing instructions for a vector processing system.

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93. Sakhin Yuli Kh.,RUX ; Artyomov Alexander M.,RUX ; Lizorkin Alexey P.,RUX ; Rudometov Vladimir V.,RUX ; Nazarov Leonid N.,RUX, Method and apparatus for packing and unpacking wide instruction word using pointers and masks to shift word syllables to.

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94. Wang,Yulun; Uecker,Darrin R.; Jordan,Charles S.; Wright,James W.; Laby,Keith Phillip; Wilson,Jeff D.; Ghoudoussi,Modjtaba, Method and apparatus for performing minimally invasive cardiac procedures.

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95. Wang,Yulun; Uecker,Darrin R.; Laby,Keith Phillip; Wilson,Jeff; Jordan,Steve; Wright,James, Method and apparatus for performing minimally invasive cardiac procedures.

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96. Wang,Yulun; Uecker,Darrin R.; Laby,Keith Phillip; Wilson,Jeff; Jordan,Steve; Wright,James, Method and apparatus for performing minimally invasive cardiac procedures.

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97. Wang, Yulun; Uecker, Darrin; Laby, Keith P.; Wilson, Jeff D.; Jordan, Charles S.; Wright, James W.; Ghodoussi, Modjtaba, Method and apparatus for performing minimally invasive surgical procedures.

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98. Yulun Wang ; Darrin Uecker ; Keith Laby ; Jeff Wilson ; Charles Jordan ; James Wright ; Modjtaba Ghodoussi, Method and apparatus for performing minimally invasive surgical procedures.

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99. Hansen, Craig; Moussouris, John, Method and software for partitioned group element selection operation.

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100. van Hook,Timothy; Hsu,Peter; Huffman,William A.; Moreton,Henry P.; Killian,Earl A., Method for providing extended precision in SIMD vector arithmetic operations.

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101. Larner Adrian (Leamington Spa GB2), Method of controlling use of resources in a data processing system by at least two processes.

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102. Koyanagi Hisao,JPX, Method of implementing vector operation using a processor chip which is provided with a vector unit.

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103. Jin, Hui; Richardson, Thomas; Novichkov, Vladimir, Methods and apparatus for encoding LDPC codes.

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104. Jin, Hui; Richardson, Tom; Novichkov, Vladimir, Methods and apparatus for encoding LDPC codes.

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105. Niemann George W. (Dallas TX), Micro-vector processor.

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106. Chastain David M. (Plano TX) Gostin Gary B. (Coppell TX), Microcode computer having dispatch and main control stores for storing the first and the remaining microinstructions of.

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107. Wallach, Steven J.; Brewer, Tony, Microprocessor architecture having alternative memory access paths.

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108. Stribaek, Morten; Kissell, Kevin D.; Paillier, Pascal, Microprocessor instructions for performing polynomial arithmetic operations.

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109. Sanchez, Dan; Uecker, Darrin; Svanidze, Oleg; Wright, James; Wang, Yulun, Microwrist system for surgical procedures.

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110. Wang, Yulun; Ghodoussi, Modjtaba; Uecker, Darrin; Wright, James; Mangaser, Amante; Mukherjee, Ranjan, Minimally invasive surgical training using robotics and tele-collaboration.

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111. Wang, Yulun; Ghodoussi, Modjtaba; Uecker, Darrin R.; Wright, James W.; Mangaser, Amante A.; Mukherjee, Ranjan, Minimally invasive surgical training using robotics and telecollaboration.

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112. Wang, Yulun; Ghodoussi, Modjtaba; Uecker, Darrin; Wright, James; Mangaser, Amante; Mukherjee, Ranjan, Minimally invasive surgical training using robotics and telecollaboration.

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113. Wang,Yulun; Ghodoussi,Modjtaba; Uecker,Darrin; Wright,James; Mangaser,Amante; Mukherjee,Ranjan, Minimally invasive surgical training using robotics and telecollaboration.

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114. Kohn Leslie D. (San Mateo CA), Modular digital computer system for storing and selecting data processing procedures and data.

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115. Wang, Yulun; Ghodoussi, Modjtaba; Uecker, Darrin; Wright, James; Mangaser, Amante, Modularity system for computer assisted surgery.

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116. Wang, Yulun; Ghodoussi, Modjtaba; Uecker, Darrin; Wright, James; Mangaser, Amante, Modularity system for computer assisted surgery.

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117. Wang, Yulun; Ghodoussi, Modjtaba; Uecker, Darrin; Wright, James; Mangaser, Amante, Modularity system for computer assisted surgery.

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118. Wang, Yulun; Ghodoussi, Modjtaba; Uecker, Darrin; Wright, James; Mangaser, Amante, Modularity system for computer assisted surgery.

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119. Wang, Yulun; Ghodoussi, Modjtaba; Uecker, Darrin; Wright, James; Mangaser, Amante, Modularity system for computer assisted surgery.

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120. Wang, Yulun; Ghodoussi, Modjtaba; Uecker, Darrin; Wright, James; Mangaser, Amante, Modularity system for computer assisted surgery.

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121. Wang,Yulun; Ghodoussi,Modjtaba; Uecker,Darrin; Wright,James; Mangaser,Amante, Modularity system for computer assisted surgery.

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122. Wang,Yulun; Jordan,Charles S.; Uecker,Darrin R., Multi-functional surgical control system and switching interface.

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123. Wang, Yulun; Jordan, Charles S.; Uecker, Darrin R., Multi-functional surgical control system switching interface.

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124. Wallach, Steven J.; Brewer, Tony, Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set.

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125. Kumar, Rajesh; Hoffman, Brian D.; Prisco, Giuseppe Maria; Larkin, David Q.; Nowlin, William C.; Moll, Frederic H.; Blumenkranz, Stephen J.; Niemeyer, Gunter D.; Salisbury, Jr., J. Kenneth; Wang, Yulun; Ghodoussi, Modjtaba; Uecker, Darrin R.; Wright, James W.; Mangaser, Amante A.; Mukherjee, Ranjan, Multi-user medical robotic system for collaboration or training in minimally invasive surgical procedures.

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126. Kumar, Rajesh; Hoffman, Brian David; Prisco, Giuseppe Maria; Larkin, David Q.; Nowlin, William C.; Moll, Frederic H.; Blumenkranz, Stephen J.; Niemeyer, Gunter D.; Salisbury, Jr., J. Kenneth; Wang, Yulun; Ghodoussi, Modjtaba; Uecker, Darrin R.; Wright, James W.; Mangaser, Amante A.; Mauherjee, Ranjan, Multi-user medical robotic system for collaboration or training in minimally invasive surgical procedures.

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127. Kumar, Rajesh; Hoffman, Brian David; Prisco, Giuseppe Maria; Larkin, David Q.; Nowlin, William C.; Moll, Frederic H.; Blumenkranz, Stephen J.; Niemeyer, Gunter D.; Salisbury, Jr., J. Kenneth; Wang, Yulun; Ghodoussi, Modjtaba; Uecker, Darrin R.; Wright, James W.; Mangaser, Amante A.; Mauherjee, Ranjan, Multi-user medical robotic system for collaboration or training in minimally invasive surgical procedures.

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128. Kumar, Rajesh; Hoffman, Brian David; Prisco, Giuseppe Maria; Larkin, David Q.; Nowlin, William C.; Moll, Frederic H.; Blumenkranz, Stephen J.; Niemeyer, Gunter D.; Salisbury, Jr., J. Kenneth; Wang, Yulun; Ghodoussi, Modjtaba; Uecker, Darrin R.; Wright, James W.; Mangaser, Amante A.; Mauherjee, Ranjan, Multi-user medical robotic system for collaboration or training in minimally invasive surgical procedures.

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129. Kumar, Rajesh; Hoffman, Brian; Prisco, Giuseppe; Larkin, David; Nowlin, William; Moll, Frederic; Blumenkranz, Stephen; Niemeyer, Gunter D; Salisbury, J. Kenneth; Wang, Yulun; Ghodoussi, Modjtaba; Uecker, Darrin; Wright, James; Mangaser, Amante; Mauherjee, Ranjan, Multi-user medical robotic system for collaboration or training in minimally invasive surgical procedures.

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130. Sanchez, Dan; Uecker, Darrin, Multifunctional handle for a medical robotic system.

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131. Sanchez, Dan; Uecker, Darrin, Multifunctional handle for a medical robotic system.

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132. Sanchez, Dan; Uecker, Darrin, Multifunctional handle for a medical robotic system.

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133. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.

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134. Brewer, Tony M.; Andrewartha, J. Michael; O'Leary, William D.; Dugan, Michael K., Multiple data channel memory module architecture.

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147. Sanchez, Dan; Black, Michael; Hammond, Scott, Pivot point arm for a robotic system used to perform a surgical procedure.

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155. Grace, Kenneth, Rigidly-linked articulating wrist with decoupled motion transmission.

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156. Grace, Kenneth, Rigidly-linked articulating wrist with decoupled motion transmission.

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159. Earle W. Jennings, III, Single precision array processor.

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160. Wang,Yulun; Uecker,Darrin, Speech interface for an automated endoscope system.

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161. Wang, Yulun; Uecker, Darrin, Speech interface for an automated endoscopic system.

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163. Ramans, Andris D.; Rosa, David J.; Falk, Volkmar, Stabilizer for robotic beating-heart surgery.

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165. Kissell, Kevin D., Substituting portion of template instruction parameter with selected virtual instruction parameter.

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166. Garg, Sanjiv; Iadonato, Kevin Ray; Nguyen, Le Trong; Wang, Johannes, Superscalar RISC instruction scheduling.

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167. Hansen, Craig; Moussouris, John; Massalin, Alexia, System and apparatus for group floating-point inflate and deflate operations.

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168. Hansen, Craig; Moussouris, John; Massalin, Alexia, System and apparatus for group floating-point inflate and deflate operations.

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169. Schiffleger Alan J., System and method for distributed multiprocessor communications.

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171. Greyzck, Terry D., System and method for managing processor-in-memory (PIM) operations.

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172. Deosaran, Trevor A.; Garg, Sanjiv; Iadonato, Kevin R., System and method for register renaming.

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173. Deosaran, Trevor A.; Garg, Sanjiv; Iadonato, Kevin R., System and method for register renaming.

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174. Wang, Johannes; Garg, Sanjiv; Deosaran, Trevor, System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor.

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175. Stephenson R. Ashley (Tewksbury MA) Normoyle Kevin B. (Ashland MA), System for transferring multiple vector data elements to and from vector memory in a single operation.

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176. Sasanka, Ruchira, System, apparatus and method for translating vector instructions.

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177. Brewer, Tony, Systems and methods for mapping a neighborhood of data to general registers of a processing element.

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178. Ghodoussi, Modjtaba; Butner, Steve E., Tele-medicine system that transmits an entire state of a subsystem.

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179. Ghodoussi, Modjtaba; Butner, Steve E., Tele-medicine system that transmits an entire state of a subsystem.

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180. Rusterholz John T. (Roseville MN) Homan Charles J. (St. Paul MN) Brown Lowell E. (Anoka MN) Bennett Donald B. (Burnsville MN) Malnati Robert J. (St. Paul MN) Hamstra James R. (Plymouth MN), Tightly coupled scientific processing system.

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181. Greyzck, Terry D., Using vector atomic memory operation to handle data of different lengths.

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182. Greyzck, Terry D., Vector atomic memory operation vector update system and method.

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183. Kinoshita Seiichiro (Tokyo JPX), Vector data processing system comprising an I/O control for each vector data processor and another I/O control for at le.

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184. Omoda Koichiro (Hadano JPX) Nagashima Shigeo (Hachioji JPX) Torii Shunichi (Kokubunji JPX), Vector data processor.

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185. Buchty,Rainer; Heintze,Nevin; Oliva,Dino P., Vector indexed memory unit and method.

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186. Kinoshita Yoshiaki (Hadano JPX) Kazama Yoshiharu (Hadano JPX) Miyamoto Shunsuke (Tokyo JPX) Omoda Koichiro (Sagamihara JPX) Nakagawa Takayuki (Kokubunji JPX), Vector operation designator.

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187. Hayashi Hideo (Tokyo JPX) Omata Makoto (Yamanashi JPX), Vector operation instruction activation controller for vector arithmetic units having arithmetic functions with differen.

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188. Drimak Edward G. (Johnson City NY), Vector processing.

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189. Nakagawa Yaoko (Hadano JPX) Ishii Koichi (Hadano JPX), Vector processing apparatus for incrementing indices of vector operands of different length according to arithmetic oper.

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190. Watanabe Tadashi (Tokyo JPX), Vector processing system.

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191. Asanovic Krste, Vector processing system with multi-operation, run-time configurable pipelines.

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192. Garcia Leslie C. (Poughkeepsie NY) Tjon-Pian-Gi David C. (Hopewell Junction NY) Tucker Stuart G. (Poughkeepsie NY) Zajac Myron W. (Poughkeepsie NY), Vector processing unit.

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193. Nagashima Shigeo (Hachioji JPX) Abe Hitoshi (Hadano JPX) Hatakeyama Yasuhiko (Hadano JPX), Vector processor.

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194. Omoda Koichiro (Sagamihara JPX) Nagashima Shigeo (Hachioji JPX), Vector processor.

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195. Inagami Yasuhiro (Kodaira JPX) Nagashima Shigeo (Hachioji JPX) Omoda Koichiro (Sagamihara JPX) Nakagawa Takayuki (Kokubunji JPX) Tanaka Teruo (Hachioji JPX), Vector processor capable of parallely executing instructions and reserving execution status order for restarting interru.

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196. Omoda Koichiro (Sagamihara JPX) Torii Shunichi (Musashino JPX) Nagashima Shigeo (Hachioji JPX) Inagami Yasuhiro (Hadano JPX) Nakagawa Takayuki (Hadano JPX), Vector processor for reordering vector data during transfer from main memory to vector registers.

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197. Beard Douglas R. (Eleva WI) Phelps Andrew E. (Eau Claire WI) Woodmansee Michael A. (Eau Claire WI) Blewett Richard G. (Altoona WI) Lohman Jeffrey A. (Eau Claire WI) Silbey Alexander A. (Eau Claire WI, Vector processor having functional unit paths of differing pipeline lengths.

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198. Hatakeyama Yasuhiko (Hadano JPX) Nagashima Shigeo (Hachioji JPX), Vector processor having pair process mode and single process mode.

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199. Tanaka Yoshikazu (Kitaadachi JPX) Torii Shunichi (Musashino JPX), Vector processor system comprised of plural vector processors.

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200. Tanaka Teruo (Kokubunji JPX) Omoda Koichiro (Sagamihara JPX) Inagami Yasuhiro (Kodaira JPX) Nakagawa Takayuki (Kokubunji JPX) Sugie Mamoru (Sayama JPX) Nagashima Shigeo (Hachioji JPX), Vector processor with vector buffer memory for read or write of vector data between vector storage and operation unit.

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201. Fossum Tryggve (Northboro MA) Manley Dwight P. (Holliston MA) McKeen Francis X. (Westboro MA) Tehranian Michael M. (Boxboro MA), Vector register system for executing plural read/write commands concurrently and independently routing data to plural re.

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202. Schiffleger Alan J. ; Gupta Ram K. ; Hsiung Christopher C., Vector shift functional unit for successively shifting operands stored in a vector register by corresponding shift counts stored in another vector register.

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203. Ansari, Ahmad R., Vector transfer system generating address error exception when vector to be transferred does not start and end on same memory page.

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204. Beard Douglas R. (Eleva WI) Phelps Andrew E. (Eau Claire WI) Woodmansee Michael A. (Eau Claire WI) Blewett Richard G. (Altoona WI) Lohman Jeffrey A. (Eau Claire WI) Silbey Alexander A. (Eau Claire WI, Vector/scalar processor with simultaneous processing and instruction cache filling.

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205. Jennings, III, Earle W., Video frame rendering engine.

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206. Kissell, Kevin D., Virtual instruction expansion using parameter selector defining logic operation on parameters for template opcode substitution.

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207. Smith James E., Virtual memory system for vector based computer systems.

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