초록 ▼

A method and apparatus for detecting cylinder malfunction by monitoring the actual rotational speed in an internal combustion engine, e.g. with an inductive transducer. This signal is compared in phase with pulses from a voltage controlled oscillator, the control voltage of which comes from an integ

A method and apparatus for detecting cylinder malfunction by monitoring the actual rotational speed in an internal combustion engine, e.g. with an inductive transducer. This signal is compared in phase with pulses from a voltage controlled oscillator, the control voltage of which comes from an integrating circuit driven by the phase comparison signal in the manner of a phase-locked loop. The VCO pulses are used to clock a shift register and the actual pulses provide the data input for the shift register. Thus, the relative arrival time of the two pulse trains determines the contents of the shift register. Decoding circuitry is used to interrogate the shift register and to actuate an output device when the contents of the register indicate an unsymmetric periodicity, caused by cylinder malfunction.

대표청구항 ▼

A method for detecting malfunctions in individual cylinders of an internal combustion engine, comprising the steps of generating first electrical pulses in synchronism with the rotation of an engine member; providing a phase comparator for generating a control signal and applying said first electric

A method for detecting malfunctions in individual cylinders of an internal combustion engine, comprising the steps of generating first electrical pulses in synchronism with the rotation of an engine member; providing a phase comparator for generating a control signal and applying said first electrical pulses to one signal input of said phase comparator; applying said control signal to a signal generator to thereby generate a train of second electrical pulses having a frequency equal to the average frequency of said first pulses and applying said second pulses to the other input of said phase comparator; providing a shift register having a data input and clock input and applying the first pulses to one of the inputs of the shift register and applying the second pulses to the other input of the shift register, thereby storing in the shift register a sequence of phase data bits indicating the sense of the relative phase difference between the first and second pulses; and triggering a warning device when all of the data bits in the stored sequence indicate the same sense of relative phase difference between the first and second pulses.