초록 ▼

An electronic circuit block for use in a timepiece comprising a circuit substrate with component-receiving portions, circuit components mounted on the component-receiving portions with terminals at the same level with the upper surfaces of the circuit components, an insulated layer made of polyimide

An electronic circuit block for use in a timepiece comprising a circuit substrate with component-receiving portions, circuit components mounted on the component-receiving portions with terminals at the same level with the upper surfaces of the circuit components, an insulated layer made of polyimide resins formed on at least a part of the circuit substrate and in gaps between the components and the component-receiving portions and a conductive pattern formed on the insulated layer after a part of the insulated layer is excluded whereby connections of components are made by said conductive pattern.

대표청구항 ▼

An electronic circuit block for use in a timepiece and for mounting circuit components having terminals such as integrated circuits, and condensers having terminals for connection in a circuit, said circuit block comprising: (a) a substrate having (b) upper and lower connection surfaces for providin

An electronic circuit block for use in a timepiece and for mounting circuit components having terminals such as integrated circuits, and condensers having terminals for connection in a circuit, said circuit block comprising: (a) a substrate having (b) upper and lower connection surfaces for providing electrical connections to said circuit components, (c) a component-receiving recess in said upper connection surface for mounting at least one circuit component in said substrate with the terminals thereof positioned on the plane of said upper connection surface, (d) an insulating layer of polyimide resin having upper and lower surfaces, said insulating layer formed on said upper connection surface of said substrate and between and over said component and said recess, the lower surface being adjacent said upper connection surface, (e) said insulating layer having excluded areas adjacent said terminals, said terminals passing through the excluded areas of said insulating layer, and (f) a conductive pattern formed on the upper surface of said insulated layer and in direct contact with said terminals.