$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Modular dynamic burn-in apparatus 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H02J-013/00
출원번호 US-0839665 (1977-10-05)
발명자 / 주소
  • Dice Charles A. (Milpitas CA)
출원인 / 주소
  • Serel Corporation (Milpitas CA 02)
인용정보 피인용 횟수 : 51  인용 특허 : 1

초록

A modular-type integrated circuit burn-in apparatus including a power supply for developing integrated circuit biasing potentials, an oven and a plurality of modules each having a plug-in pattern generator for generating integrated circuit exercising signals of a type programmed by a first plug-in h

대표청구항

A system for generating exercising signals for an integrated circuit burn-in apparatus comprising: power supply means for developing integrated circuit biasing potentials; an oven for receiving a plurality of integrated circuits to be burned-in; a plurality of modules each having a plug-in pattern g

이 특허에 인용된 특허 (1)

  1. Meany David P. (Anaheim CA), Universal burn-in fixture.

이 특허를 인용한 특허 (51)

  1. Milby Gregory H. (San Diego CA) Daniel Richard A. (Escondido CA) Rostek Paul M. (San Diego CA), Apparatus for assisting in the connection and disconnection of a board with an energized circuit.
  2. Eliashberg Victor M. ; Prakash Kombupalayam M., Apparatus for testing an integrated circuit in an oven during burn-in.
  3. Eliashberg Victor M. ; Prakash Kombupalayam M., Apparatus for testing an integrated circuit in an oven during burn-in.
  4. Eliashberg Victor M. ; Prakash Kombupalayam M., Apparatus for testing an integrated circuit in an oven during burn-in.
  5. Victor M. Eliashberg ; Kombupalayam M. Prakash, Apparatus for testing an integrated circuit in an oven during burn-in.
  6. Cutright Robert A. (Holland MI) Briggs Mark W. (Holland MI) Bouwman George J. (Hamilton MI), Apparatus for use in testing circuit boards.
  7. Hamilton Harold E. (Minneapolis MN), Apparatus providing signals for burn-in of integrated circuits.
  8. Yong Jaimsomporn TH; Surapol Phunyaphinunt TH; Tanawat Boutngam TH, Automated protection of IC devices from EOS (electro over stress) damage due to an undesired DC transient.
  9. Hamilton Harold E. ; Tremmel Tom A. ; Bloch Brian R., Burn-in board support frame having inserter and ejector bars for racks of burn-in boards.
  10. Hamilton, Harold E.; Conroy, Chad M., Cooling air flow control valve for burn-in system.
  11. Hamilton,Harold E.; Conroy,Chad M., Cooling air flow control valve for burn-in system.
  12. Zbinden Terry B. (Maple Grove MN), Detection of catastrophic failure of dielectric, improper connection, and temperature of a printed circuit assembly via.
  13. Terao Masashi,JPX, Device testing apparatus.
  14. Kilpatrick Robert A. (Santa Clara CA) Hefner Sherry M. (San Jose CA), Dual configuration connector port for burn-in systems.
  15. Stutzman, A. Jay; Cram, Daniel P., Electrical testing apparatus having masked sockets and associated systems and methods.
  16. Magnuson Vernon P. (Canoga Park CA), Environmentally controlled media defect detection system for Winchester disk drives.
  17. Lou, Choon Leong; Wang, Li Min; Lau, Yi Ming; Chen, Ho Yeh, Heating apparatus for semiconductor devices.
  18. Casa Gene E. (Ruby NY) Gernon Joseph W. (Kingston NY), High density circuit assembly.
  19. Phillip J. Etter, IC Device burn-in method and apparatus.
  20. Petrich Dennis M. (Minnetonka MN) Amick Christopher G. (Mahtomedi MN) Gruenenwald Stanley L. (Blaine MN), Integrated circuit test apparatus test head.
  21. Charruau Stephane (Paris FRX), Integrated-circuit support device employed in a system for selecting high-reliability integrated circuits.
  22. Keith Robinson, Load board socket adapter and interface method.
  23. Robinson, Keith, Load board socket adapter and interface method.
  24. Robinson,Keith, Load board socket adapter and interface method.
  25. Yokoi Satoru (Osaka JPX) Kondo Hirokazu (Osaka JPX), Load testing apparatus for electronic components.
  26. Co, Ramon S., Local heating of memory modules tested on a multi-motherboard tester.
  27. Friedrich Stadelmayer ; T. Edward States ; John Soenderby ; Francesco Sacca, Method and apparatus for testing printed circuit board assemblies.
  28. Wood Alan G. (Boise ID) Farnworth Warren M. (Nampa ID) Akram Salman (Boise ID) Hembree David R. (Boise ID), Method and apparatus for testing unpackaged semiconductor dice.
  29. Wood Alan G. ; Farnworth Warren M. ; Akram Salman ; Hembree David R., Method and apparatus for testing unpackaged semiconductor dice.
  30. Siddiqui, Shakeel M.; Tymofyeyev, Vadim, Method and apparatus to provide a burn-in board with increased monitoring capacity.
  31. Siddiqui,Shakeel M.; Tymofyeyev,Vadim, Method and apparatus to provide a burn-in board with increased monitoring capacity.
  32. Yong Jaimsomporn TH; Tanawat Boutngam TH; Narupon Tabtimted TH, Method and system for adapting burn-in boards to multiple burn-in systems.
  33. Zink Anthony J. ; Kelly Timothy J., Method for testing circuit board assemblies.
  34. Sharpes Michael J. ; Totorica Robert L., Modular design for an IC testing burn-in oven.
  35. Michael J. Sharpes ; Robert L. Totorica, Modular design for an integrated circuit testing apparatus.
  36. Sharpes Michael J. ; Totorica Robert L., Modular design for an integrated circuit testing apparatus.
  37. Rignall Michael W. (Dursley GB3), Oven for the burn-in of integrated circuits.
  38. Anderson Daniel Joseph, PC card test and configuration connector.
  39. Varadi, Andrew G.; Maghribi, Walid H., Process of performing burn-in and parallel functional testing of integrated circuit memories in an environmental chamber.
  40. Kenji Yoshida JP; Takashi Naito JP; Shigeru Murayama JP; Katsuhiko Sakamoto JP; Takashi Masaki JP, Semiconductor component mounting apparatus.
  41. Yoshida Kenji,JPX ; Naito Takashi,JPX ; Murayama Shigeru,JPX ; Sakamoto Katsuhiko,JPX ; Masaki Takashi,JPX, Semiconductor component mounting apparatus.
  42. Hamilton, Harold E.; Conroy, Chad M.; Bloch, Brian R., Shutters for burn-in-board connector openings.
  43. Casanova Wayne J. (Rochester MN) Dimmick Roger F. (Rochester MN) Hall William A. (Rochester MN) Homan Lester C. (Rochester MN) Lukes Frank J. (Rochester MN) Martin Bradley L. (Byron MN) Mosley Claude, System cable assembly and component packaging.
  44. Gunn, Bradley R.; Calderon, Alberto J.; Jovanovic, Jovan; Hendrickson, David S., System for burn-in testing of electronic devices.
  45. Gunn,Bradley R.; Calderon,Alberto J.; Jovanovic,Jovan; Hendrickson,David S., System for burn-in testing of electronic devices.
  46. Horii Ryogo,JPX, Test fixture for circuit component.
  47. Hirschmann, Peter, Test head assembly.
  48. Saito Hideki,JPX ; Takeuchi Kunio,JPX ; Yajima Nobuyuki,JPX ; Yanagi Takeyuki,JPX, Test head for semiconductor tester.
  49. Weber,Frank; Frankowsky,Gerd, Test system for testing integrated chips and an adapter element for a test system.
  50. Hsu Kai Yang, Testing electronic devices.
  51. Yoshizaki Tsutomu (Yokosuka JPX), Testing equipment for electric components.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로