초록 ▼

An improved READ/WRITE circuit for a memory array of cells arranged in rows and columns, where each cell is coupled to a bit line via the conduction path of a single gating transistor which conducts in the source follower mode for one binary condition. The circuit includes a voltage multiplying circ

An improved READ/WRITE circuit for a memory array of cells arranged in rows and columns, where each cell is coupled to a bit line via the conduction path of a single gating transistor which conducts in the source follower mode for one binary condition. The circuit includes a voltage multiplying circuit having an output at which is selectively produced either a read voltage, or a write voltage of significantly greater amplitude than the read voltage. The output of the voltage multiplying circuit is coupled via a level shifting decoder circuit, which passes either the read or the write voltage, to the control electrodes of selected gating transistors. The read voltage applied to the control electrode of a gating transistor turns it on just enough to enable the non-destructive-readout (NDRO) of the contents of its associated memory cell. The application of the write voltage to the control electrode of a gating transistor overdrives it into conduction, enabling information to be easily and safely written into its associated memory cell even at low power supply voltages.

대표청구항 ▼

In combination with a memory cell having an input-output (I/O) point and a single gating transistor whose conduction path is connected between said I/O point and a bit line, means for writing information into said cell and means for non-destructively reading the contents of the memory cell comprisin

In combination with a memory cell having an input-output (I/O) point and a single gating transistor whose conduction path is connected between said I/O point and a bit line, means for writing information into said cell and means for non-destructively reading the contents of the memory cell comprising: first and second power terminals for the application therebetween of an operating potential; a voltage multiplier circuit connected between said first and second power terminals having an output node at which is selectively produced either a read voltage which is approximately equal in amplitude to said operating potential or a write voltage which is substantially greater in amplitude and of same polarity as said read voltage; and a selectively decoded level shift circuit connected between said output node and the control electrode of said gating transistor for, when selected, coupling the voltage at said output node to the control electrode of said gating transistor.