초록 ▼

A rapid-response overload protector interposed between a voltage source and a load powered thereby, the protector effectively decoupling the load from the source when the current drawn thereby exceeds a predetermined limit indicative of an overload condition. The protector includes an automatic rese

A rapid-response overload protector interposed between a voltage source and a load powered thereby, the protector effectively decoupling the load from the source when the current drawn thereby exceeds a predetermined limit indicative of an overload condition. The protector includes an automatic resetting stage that periodically samples the state of the load and acts to restore the normal supply of current thereto when the current drawn by the load during the sampling interval falls below the limit.

대표청구항 ▼

An overload protector interposed between a d-c voltage source and a load supplied thereby, said protector comprising: A. a current-control network constituted by a pass transistor connected in series with a current-limiting resistor between the source and the load; B. a latching network connected ac

An overload protector interposed between a d-c voltage source and a load supplied thereby, said protector comprising: A. a current-control network constituted by a pass transistor connected in series with a current-limiting resistor between the source and the load; B. a latching network connected across the control network formed by a resistor in series with a latching transistor; C. a driver transistor connected to the base of the pass transistor, the base of the driver transistor being connected to the junction of said resistor and latching transistor of said latching network; D. a voltage divider connected across the control network, said divider formed by two resistors connected in series and having a tap connected to the base of the latching transistor to render the latching transistor conductive when the voltage across the divider is high, said driver transistor and said pass transistor being conductive uner normal load conditions below a predetermined limit to supply current to the load, in which condition the voltage across the divider is low and said latching transistor is then non-conductive, the voltage drop across said current-limiting resistor reaching a value when said current exceeds said limit under overload conditions to bias said pass transistor to cut-off, at which point the voltage drop across said divider becomes high to apply a bias to the base of said latching transistor to render it conductive and thereby bias the driver transistor to its “off”state, which driver transistor then biases the pass transistor to its “off”state; and E. an automatic resetting stage coupled to said control network to periodically sample the state of said load and to restore said pass transistor to its “on state”and to restore the normal supply of current to said load when the current drawn during a sampling interval falls below said limit, said resetting stage including a slow speed pulser which is connected to said control network through a diode which is rendered conductive to activate said pulses when said pass transistor is rendered non-conductive, which applies a pulse to the base of the latching transistor when an overload condition is sampled to render said latching transistor non-conductive and thereby allow current to again flow in the current-limiting resistor, said pulses being formed by a pulse transistor connected to an R-C network which is charged through said conductive diode and discharged by said pulse transistor when the charge attains a critical value to produce a pulse, said pulse being applied to the base of the latching transistor through a capacitor.