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Level shift circuit 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-005/02
  • H03K-003/353
  • H03K-017/10
출원번호 US-0948509 (1978-10-04)
발명자 / 주소
  • Stewart Roger G. (Neshanic Station NJ)
출원인 / 주소
  • RCA Corporation (New York NY 02)
인용정보 피인용 횟수 : 43  인용 특허 : 6

초록

A gating means, biased to pass current only during signal transitions, transfers binary signals from an input signal source to a latch circuit when the signal source and the latch are operated at similar voltages. Following data transfer, the operating voltage across the latch is increased. The volt

대표청구항

A level shift circuit comprising: an input point at which are generated data signals varying in amplitude between a first voltage level and a second voltage level; a latch circuit having at least one stable state; a gating transistor having a conduction path and a control electrode, the conduction p

이 특허에 인용된 특허 (6)

  1. Cricchi ; James R. ; Fitzpatrick ; Michael D., High speed, radiation hard complementary MOS capacitive voltage level shift circuit.
  2. Alaspa Allan A. (Tempe AZ) Beutler Robert R. (Tempe AZ), Integrated circuit having internal main supply voltage regulator.
  3. Dingwall Andrew Gordon Francis (Somerville NJ) Rosenthal Bruce David (Mountain View CA), Level shift circuit.
  4. Stewart ; Roger Green, Level shift circuit.
  5. Fox Jeffrey R. (Waltham MA) Walsh William D. (Franklin MA), Logic level converter.
  6. Rosenthal Bruce David (Highland Park NJ) Dingwall Andrew Gordon Francis (Somerville NJ), Voltage amplitude multiplying circuits.

이 특허를 인용한 특허 (43)

  1. Terry C. Coughlin, Jr. ; Joseph M. Milewski ; Akio Miyoshi JP; Loc Khac Nguyen, 5V-tolerant receiver for low voltage CMOS technologies.
  2. Wacyk Ihor T. (Bridgewater NJ), Actively controlled input buffer.
  3. Chao Hu H. (Pleasantville West NY) Lu Nicky C. (Yorktown Heights NY), Boost word-line clock and decoder-driver circuits in semiconductor memories.
  4. Goodwin John J. (Pleasantville NY) Lu Nicky C. (Yorktown Heights NY), Boosting word-line clock circuit for semiconductor memory.
  5. Higuchi Mitsuo (Tokyo JPX), CMIS Level shift circuit.
  6. Runaldue Thomas J. (San Jose CA), CMOS clamp circuits.
  7. Schrenk Hartmut (Haar DEX), CMOS-inverter.
  8. Atsumi Shigeru (Tokyo JPX) Tanaka Sumio (Tokyo JPX), Circuit for changing the voltage level of binary signals.
  9. Foss, Richard C.; Gillingham, Peter B.; Harland, Robert F.; Lines, Valerie L., DRAM boosted voltage supply.
  10. Runaldue Thomas J. (San Jose CA) Plants William (Santa Clara CA), Dual port memory, such as used in color lookup tables for video systems.
  11. Lines, Valerie L., Dynamic memory word line driver scheme.
  12. Lines, Valerie L., Dynamic memory word line driver scheme.
  13. Lines,Valerie L., Dynamic memory word line driver scheme.
  14. Dingwall Andrew G. F. (Bridgewater NJ), Electronic circuits and structures employing enhancement and depletion type IGFETs.
  15. Spence John R., Five volt tolerant protection circuit.
  16. Madhu Raghava (Trichur INX) Kengeri Subramani (Norwood MA), High noise-margin TTL buffer circuit capable of operation with wide variation in the power supply voltage.
  17. Cheung Sammy ; Lam John ; Patel Rakesh ; Ngai Tony, High performance output buffer.
  18. Sanwo Ikuo J. (San Marcos CA) Donahue James A. (Great Falls MT), High speed CMOS backpanel transceiver.
  19. Vinal Albert W. (Cary NC), High speed complementary field effect transistor logic circuits.
  20. Higashisaka Norio (Hyogo JPX), High speed logic circuit having output feedback.
  21. Terry C. Coughlin, Jr. ; Joseph M. Milewski ; Loc K. Nguyen ; Douglas W. Stout, High voltage tolerant receivers.
  22. Plus Dora (Borough of South Bound Brook NJ), High-speed voltage level shift circuit.
  23. Atherton James H. (Freeport IL), Input buffer circuit.
  24. Tsugaru Kazunori (Yokohama JPX) Sugimoto Yasuhiro (Yokohama JPX), Level conversion circuit.
  25. Atherton James H. (Flemington NJ) Dreisbach William C. (Baldwinsville NY), Level shift circuit.
  26. Hsieh Peter K. (Parsippany NJ) Vaccarella Richard M. (Raritan NJ), Level shift circuit.
  27. Gentile Carmine J. (Hightstown NJ) Hagge Melvin L. (Bridgewater NJ) Croes Robert C. (Nijmegen NLX), Level shift interface circuit.
  28. Terletzki, Hartmud; Frankowsky, Gerd, Level-shifting circuitry having “high” output impedance during disable mode.
  29. Chan Yiu-Fai (Saratoga CA) Evans Allen L. (Colorado Springs CO), Monolithic CMOS low power digital level shifter.
  30. Austin John Stephen (Burlington VT) Stout Douglas Willard (Milton VT), Off-chip driver for mixed voltage applications.
  31. Shubat Alexander (Newark CA) Sani Barmak (Cupertino CA), Output circuit for driving a memory device output lead including a three-state inverting buffer and a transfer gate coup.
  32. Masleid, Robert Paul, Power efficient multiplexer.
  33. Masleid, Robert Paul, Power efficient multiplexer.
  34. Masleid, Robert Paul, Power efficient multiplexer.
  35. Stewart Roger G. (Neshanic Station NJ), Power gated decoding.
  36. Morgan ; Jr. James V. (Emmaus PA) Offord Glen E. (Bethlehem PA), Programmable logic level input buffer.
  37. Kim Chang-Hyun (Seoul KRX) Choi Won-Tae (Busan KRX), Semiconductor device having a time delay function.
  38. Stewart Roger G. (Neshanic Station NJ), Sense amplifiers.
  39. Hung, Cheng-Hsien; Lin, Yu-Ling, System and method for persistent ID flag for RFID applications.
  40. Noufer Glenn E. (Austin TX) Donoghue William J. (Round Rock TX), TTL to CMOS input buffer.
  41. Hollingsworth Richard J. (Princeton NJ), Two input sense circuit.
  42. Raghunathan Kuppuswamy (Austin TX), Voltage translating circuit.
  43. Dhong Sang H. (Mahopac NY) Hwang Wei (Armonk NY) Lu Nicky C. (Yorktown Heights NY), Wordline voltage boosting circuits for complementary MOSFET dynamic memories.
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