초록 ▼

A dynamic slicing compensator for attenuated pulse width modulated signals, for use at the receiving end of a transmission line which comprises a voltage comparator the negative input of which is connected to the end of the transmission line. A negative peak riding circuit is provided with sufficien

A dynamic slicing compensator for attenuated pulse width modulated signals, for use at the receiving end of a transmission line which comprises a voltage comparator the negative input of which is connected to the end of the transmission line. A negative peak riding circuit is provided with sufficient time delay to substantially follow the negative peaks of the pulse width modulation signals. A reference or slicing voltage is provided, preferably approximately midway between the negative peaks and the baseline. This reference voltage is connected to the positive input of the comparator. As the attenuation and distortion increases, the negative peaks become smaller and the reference voltage similarly becomes smaller, maintaining a substantially constant ratio to the value of the negative peaks.

대표청구항 ▼

Dynamic slicing compenation means for detecting attenuated pulse width modulation signals, in noise, at the receiving end of a transmission means, comprising; (a) comparator means having a non-inverting first input and a an inverting second input, and an output; and means to connect the second input

Dynamic slicing compenation means for detecting attenuated pulse width modulation signals, in noise, at the receiving end of a transmission means, comprising; (a) comparator means having a non-inverting first input and a an inverting second input, and an output; and means to connect the second input to said receiving end of said transmission means; (b) a voltage source of selected magnitude of voltage connected through a resistor of selected magnitude of resistance, to said receiving end of said transmission means; (c) a bypass circuit connected from said voltage source to said receiving end, comprising in series; 1. a first resistor to a first junction point; 2. a second resistor from said first junction point to a second junction point; 3. a third resistor connected from said second junction point through a diode to said receiving end; (d) a capacitor of selected magnitude of capacitance connected from said second junction point to ground; and (e) said first junction connected to the first input of said comparator.