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Electronic package assembly method 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-003/06
  • H05K-003/10
  • H05K-003/34
출원번호 US-0002473 (1979-01-10)
발명자 / 주소
  • Gazdik Charles E. (Endicott NY) McBride Donald G. (Binghamton NY)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 43  인용 특허 : 1

초록

A method for making an electronic package assembly of the type having an insulator pin carrier, a thin, i.e. substantially five microns, flexible printed circuit (PC) polyimide member having printed circuit conductors bonded to the heads of the pins of the carrier, and one or more integrated circuit

대표청구항

The method for making at least one electronic package assembly, said assembly having at least an insulator pin carrier member, plural conductive elongated pluggable pins carried by said member, each of said pins being extended through said member to provide first and second extensions past first and

이 특허에 인용된 특허 (1)

  1. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.

이 특허를 인용한 특허 (43)

  1. Groves Henry T. (Camarillo CA) Hultberg Frank R. (Tujunga CA) Klacks John A. (Canoga Park CA), Case assembly for stacking integrated circuit packages.
  2. Tsuji Mutsuo (Tokyo JPX), Chip carrier.
  3. Werbizky George G. (Vestal NY), Circuit module with separate signal and power connectors.
  4. Grabbe Dimitry G. (Middletown PA), Compliant interconnection and method therefor.
  5. P. R. Patel ; Yuan-Liang Li ; David G. Figueroa ; Shamala Chickamenahalli ; Huong T. Do, Dual-socket interposer and method of fabrication therefor.
  6. P. R. Patel ; Yuan-Liang Li ; David G. Figueroa ; Shamala Chickamenahalli ; Huong T. Do, Dual-socket interposer and method of fabrication therefor.
  7. Coon,Warren, ESD protected suspension interconnect.
  8. Jones Alan L. (Endwell NY) Synder Keith A. (Vestal NY), Electronic package with a device positioned above a substrate by suction force between the device and heat sink.
  9. Brown Michael B. (Binghamton NY) Ebert William S. (Endicott NY) Olson Leonard T. (Endwell NY) Sloma Richard R. (Endicott NY), Electronic package with integrated distributed decoupling capacitors.
  10. Khandros Igor Y. ; Eldridge Benjamin N. ; Mathieu Gaetan L., Fabricating interconnects and tips using sacrificial substrates.
  11. McBride Donald G. (Binghamton NY) Ellis Theron L. (Vestal NY), Flexible carrier for an electronic device.
  12. McBride Donald G. (Binghamton NY) Ellis Theron L. (Vestal NY), Flexible carrier for an electronic device.
  13. Dodsworth, Robert S.; Scheibner, John B.; Zhang, Ke; Ee, Chee Tat; Mok, Juang Meng; Lee, Yong Peng, Flexible circuit with electrostatic damage limiting feature.
  14. Scheibner,John B.; Zhang,Ke; Ee,Chee Tat; Mok,Juang Meng; Lee,Yong Peng, Flexible circuit with electrostatic damage limiting feature.
  15. Robert S. Dodsworth, Flexible circuit with electrostatic damage limiting feature and method of manufacture.
  16. Yang Rui ; Truong Thach G. ; Mooney Justine A. ; David Moses M., Flexible circuits and carriers and process for manufacture.
  17. Yang Rui, Flexible circuits with static discharge protection and process for manufacture.
  18. Clementi Robert J. (Binghamton NY) Gazdik Charles E. (Endicott NY) Lafer William (Chenango Bridge NY) Lovesky Roy L. (Vestal NY) McBride Donald G. (Binghamton NY) Munson Joel V. (Port Crane NY) Skarv, Flexible film semiconductor chip carrier.
  19. Albrechta Stanley M. (Binghamton NY) Burns Francis C. (Endicott NY) Carden Gary R. (Endwell NY) Chen William T. (Endicott NY) Gresko Andrew R. (Binghamton NY) Kaufman John J. (Windsor NY) Skarvinko E, Flexible supporting cable for an electronic device and method of making same.
  20. Gazdik Charles E. (Endicott NY) McBride Donald G. (Binghamton NY) Seraphim Donald P. (Vestal NY) Toole Patrick A. (Westport CT), Full panel electronic packaging structure.
  21. Eberle, Michael J.; Stephens, Douglas N.; Rizzuti, Gary; Kiepen, Horst; Hodjicostis, Andreas, High resolution intravascular ultrasound transducer assembly having a flexible substrate.
  22. Eberle,Michael J.; Stephens,Douglas N.; Rizzuti,Gary; Kiepen,Horst F.; Hodjicostis,Andreas, High resolution intravascular ultrasound transducer assembly having a flexible substrate.
  23. Hakey, Mark C.; Holmes, Steven J.; Horak, David V.; Linde, Harold G.; Sprogis, Edmund J., Integrated semiconductor device having co-planar device surfaces.
  24. Khandros Igor Y. ; Mathieu Gaetan L., Interconnection substrates with resilient contact structures on both sides.
  25. Bhattacharya Somnath (Wappingers Falls NY) Chance Dudley A. (Danbury CT) Koopman Nicholas G. (Hopewell Junction NY) Ray Sudipta K. (Wappingers Falls NY), Layered metal film structures for LSI chip carriers adapted for solder bonding and wire bonding.
  26. Desai Kishor V. (Vestal NY) Kohn Harold (Endwell NY), Method for mounting a flexible film semiconductor chip carrier on a circuitized substrate.
  27. Hakey, Mark C.; Holmes, Steven J.; Horak, David V.; Linde, Harold G.; Sprogis, Edmund J., Method of assembling a plurality of semiconductor devices having different thickness.
  28. Kim,Jae young, Method of connecting signal lines, a printed circuit board assembly and electronic apparatus having the same.
  29. Serizawa, Yasuyoshi; Iwasaki, Kenji; Kubota, Minoru; Nishitani, Keizo, Method of manufacturing a circuit unit.
  30. Kimura Mitsuru (Tokyo JPX) Nakakita Shoji (Tokyo JPX), Method of manufacturing a multichip package with increased adhesive strength.
  31. Thaveeprungsriporn,Visit; Hu,Szu Han, Method to form electrostatic discharge protection on flexible circuits using a diamond-like carbon material.
  32. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure.
  33. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Microelectronic contact structure and method of making same.
  34. Wen-chou Vincent Wang ; Thomas J. Massingill ; Yasuhito Takahashi ; Lei Zhang, Modules with pins and methods for making modules with pins.
  35. Takenaka Takaji (Hadano JPX) Netsu Tositada (Hadano JPX) Shigi Hidetaka (Hadano JPX) Yamamoto Masakazu (Kodaira JPX), Multi-chip module structure.
  36. Pasch Nicholas F., Multiple pin die package.
  37. Burgess Allan C. (Yorktown Heights NY) Lussow Robert O. (Hopewell Junction NY) Melvin George E. (Poughkeepsie NY), Multiple voltage integrated circuit packaging substrate.
  38. Laakso Carl W. (Portland OR) Reagan John J. (Beaverton OR) Beckman Robert L. (Beaverton OR), Polyimide embedded conductor process.
  39. Eldridge, Benjamin N.; Grube, Gary W.; Khandros, Igor Y.; Mathieu, Gaetan L., Probe card assembly and kit, and methods of making same.
  40. Pasch Nicholas F., Process of fabricating an integrated circuit die package having a plurality of pins.
  41. Ogihara Satoru (Hitachi JPX) Numata Shunichi (Hitachi JPX) Miyazaki Kunio (Hitachi JPX) Yokoyama Takashi (Hitachi JPX) Takahashi Ken (Ibaraki JPX) Soga Tasao (Hitachi JPX) Yamada Kazuji (Hitachi JPX), Semiconductor chip module.
  42. Dozier ; II Thomas H. ; Khandros Igor Y., Solder preforms.
  43. Jones Robert E. (Saint Peters MO), Surface mounted component adaptor for interconnecting of surface mounted circuit components.
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