초록 ▼

An instruction set modifier register, comprising one or more bistable latches which are loadable under program control, is provided for use in a processor in conjunction with an instruction register. An instruction decoding circuit and an instruction execution control logic circuit, responsive to bo

An instruction set modifier register, comprising one or more bistable latches which are loadable under program control, is provided for use in a processor in conjunction with an instruction register. An instruction decoding circuit and an instruction execution control logic circuit, responsive to both the instruction register and the instruction set modifier register, generate a first set of control signal combinations corresponding to a first instruction set when the instruction set modifier register is in a first state and generate a second set of control signal combinations corresponding to a second instruction set when the instruction set modifier register is in a second state. The processor is thus able to execute more than one set of instructions, utilizing the same instruction decoding circuitry and instruction execution control logic circuitry.

대표청구항 ▼

In a processor comprising a data bus, a plurality of registers and logic circuits, including an instruction register coupled to said data bus for temporarily storing an individual one of a plurality of instructions from two or more instruction sets, and an instruction decoding and control circuit re

In a processor comprising a data bus, a plurality of registers and logic circuits, including an instruction register coupled to said data bus for temporarily storing an individual one of a plurality of instructions from two or more instruction sets, and an instruction decoding and control circuit responsive to said instruction register for decoding the contents of said instruction register and having a plurality of control lines for controlling the operation of said plurality of registers and logic circuits in accordance with said instructions, said processor further comprising: an instruction set modifier register having a plurality of states each corresponding to one of said instruction sets, said instruction decoding and control circuit being responsive to said instruction set modifier register for activating the same ones of said plurality of control lines when any one of a plurality of different instruction words, each from a different instruction set and representing an instruction which is common to each of said instruction sets, is stored in said instruction register, provided that the state of said instruction set modifier register corresponds to that instruction set containing said any one instruction word.