초록 ▼

A programmable sequential logic circuit processes data according to a program containing instructions of different lengths, each instruction composed of one or several words. The sequential logic circuit comprises a memory containing the instructions and data words, an arithmetic and logical process

A programmable sequential logic circuit processes data according to a program containing instructions of different lengths, each instruction composed of one or several words. The sequential logic circuit comprises a memory containing the instructions and data words, an arithmetic and logical processing unit (ALU), and an instruction register for temporarily storing an instruction word read from the memory. An adder is connected to index the contents of address registers by adding the contents of one of a plurality of data registers. A system clock circuit driven by a clock and an operation code in the instruction register to control the operation of the sequential logic circuit. Access to the ALU is through an input multiplexer inputs of which are connected to the output of the memory and the outputs of the data registers and of the address registers. The output of the ALU is connected to an output bus via a circuit having outputs which adopt a high impedance state when they are not enabled. The output bus is also connected to the inputs of the memory and of the data registers. Complete processing of an instruction according to the instruction word temporarily stored in the instruction register is performed in a plurality of phases under the control of the system clock circuit. A first portion of the plurality of phases is devoted to acquisition of one or several data or instruction words, and the second portion is devoted to the execution of an operation by the ALU according to the operation code maintained in the instruction word stored in the instruction register.

대표청구항 ▼

A programmable sequential logic circuit for the processing of data according to a program containing instructions of different lengths each instruction composed of one or several instruction words, said sequential logic circuit comprising: a memory containing instructions and data words, an arithmet

A programmable sequential logic circuit for the processing of data according to a program containing instructions of different lengths each instruction composed of one or several instruction words, said sequential logic circuit comprising: a memory containing instructions and data words, an arithmetic and logical processing unit (ALU), an instruction register for temporarily storing an instruction word from said memory, a plurality of data registers and address registers, an adder connected to index the contents of either of said address registers by adding the contents of one of said data registers to either of said address registers, a clock driving a system clock circuit which is additionly responsive to an operation code in driving said instruction register to control the operation of said sequential logic circuit, an input multiplexer through which access to said ALU is provided wherein inputs of said input multiplexer are connected to the outputs of said memory, the outputs of said data registers and the outputs of said address registers, an output bus, the output of said ALU being connected to said output bus via a circuit having outputs which adopt a high impedance state when they are not enabled, said output bus connecting elsewhere to the inputs of said memory and of said data registers, and wherein complete processing according to said instruction word temporarily stored in said instruction register is performed in a plurality of phases under the control of said system clock circuit, a first portion of said plurality of phases being devoted to the acquisition of one or several data or instruction words, and a second portion being devoted to the execution of an operation by said ALU according to an operation code contained in said instruction word stored in said instruction register.