초록 ▼

A system for performing frequency division of a high frequency signal by intermittent operation of a frequency dividing counter circuit and by a phase lock loop circuit, in which phase lock is periodically achieved with an output of the counter circuit. Phase lock loop circuit is of novel design whi

A system for performing frequency division of a high frequency signal by intermittent operation of a frequency dividing counter circuit and by a phase lock loop circuit, in which phase lock is periodically achieved with an output of the counter circuit. Phase lock loop circuit is of novel design which provides exact phase lock without cyclic variations from the reference phase.

대표청구항 ▼

A frequency division system for producing a phase locked signal of relatively low frequency which is synchronized in phase with a signal of relatively high frequency and whose frequency is an integral submultiple of said relatively high frequency, comprising: frequency divider circuit means responsi

A frequency division system for producing a phase locked signal of relatively low frequency which is synchronized in phase with a signal of relatively high frequency and whose frequency is an integral submultiple of said relatively high frequency, comprising: frequency divider circuit means responsive to said relatively high frequency signal for producing a reference signal of said relatively low frequency; a voltage controlled oscillator circuit for generating said phase locked signal, comprising a first control element for controlling the frequency of said phase locked signal and a second control element for controlling the phase of said phase locked signal in an instantaneous manner; a phase comparator circuit for comparing the phase of said phase locked signal and the phase of said reference signal and for producing a first control signal if the phase of said phase locked signal is lagging that of said reference signal and for also producing a second control signal if the phase of said phase locked signal is leading the phase of said reference signal, whereby one of said first and second control signals is applied to said second control element of said voltage controlled oscillator circuit to cause the phase of said phase locked signal to come into coincidence with said reference signal phase; and a charge pump circuit comprising a capacitor, charge control means responsive to said first control signal for increasing the amount of charge in said capacitor and discharge control means responsive to said second control signal for decreasing the amount of charge in said capacitor, the voltage appearing across said capacitor being applied to said first control element of said voltage controlled oscillator circuit so as to cause the frequency and phase of said phase locked signal to come into coincidence with the frequency and phase of said reference signal.