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Process for forming low-reactance interconnections on semiconductors 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/288
출원번호 US-0108064 (1979-12-28)
발명자 / 주소
  • Parks Earl L. (Liverpool NY) Zaidel Simon A. (Liverpool NY)
출원인 / 주소
  • General Electric Company (Syracuse NY 02)
인용정보 피인용 횟수 : 24  인용 특허 : 4

초록

Several methods are disclosed for forming an air gap between crossing thin film conductors utilized to interconnect electronic components on a substrate. Each of the methods involves the use of photolithographic techniques to form overpassing conductors on a support material covering the overpassed

대표청구항

A method of forming a conductive bridge connecting selected ones of a plurality of thin film conductors located on a substrate comprising: A. applying a layer of photosensitive material to the conductors and the substrate, said layer being of a thickness equal to the desired height of the bridges; B

이 특허에 인용된 특허 (4)

  1. Debiec Richard P. (LaGrange Park IL) Wydra William T. (Darien IL), Additive method of forming circuit crossovers.
  2. Lesh ; deceased Nathan George (LATE OF Bethlehem PA) BY Merchants National Bank of Allentown ; executor (Allentown PA) Morabito Joseph Michael (Bethlehem PA) Thomas ; III John Henry (Pickerington OH), Conduction system for thin film and hybrid integrated circuits.
  3. Berry Robert W. (Bethlehem PA) Feldman David (Allentown PA) Pfahnl Arnold (Allentown PA), Crossover structure for microelectronic circuits.
  4. Lesh ; deceased Nathan George (LATE OF Bethlehem PA) Ketterer ; executor by William B. (Allentown PA) Morabito Joseph Michael (Bethlehem PA) Thomas ; III John Henry (Pickerington OH), Method of forming crossover connections.

이 특허를 인용한 특허 (24)

  1. Andrew Z. Glovatsky ; Thomas Krautheim ; Robert E. Belke, Jr. ; Vivek Amir Jairazbhoy ; Cuong V. Pham, Electrical circuit board and a method for making the same.
  2. Lee Kyu-Woong (Arlington MA) Durschlag Mark S. (Natick MA) Day John (Lexington MA), Evaporated thick metal and airbridge interconnects and method of manufacture.
  3. Orbach Zvi (Haifa ILX) Janai Meir I. (Haifa ILX), Fabrication of customized integrated circuits.
  4. Moyer Curtis D. ; Smith Peter A. ; Reuss Robert H. ; Trottier Troy A. ; Voight Steven A. ; Carrillo Diane A. ; Nordquist Kevin J. ; Jacobs David W. ; Tobin Kathleen A., Field emission device having a vacuum bridge focusing structure and method.
  5. McNie, Mark E., Formation of a bridge in a micro-device.
  6. Alan R. Reinberg, Integrated circuit having a void between adjacent conductive lines.
  7. Reinberg Alan R., Integrated circuit having a void between adjacent conductive lines.
  8. Robert Lee Lewis ; Robert David Sebesta ; Daniel Martin Waits, Method for connecting an electrical device to a circuit substrate.
  9. Kaanta Carter W. (Colchester VT) Roberts Stanley (Burlington VT), Method for providing improved insulation in VLSI and ULSI circuits.
  10. Goenka Lakhi Nandlal ; Paruchuri Mohan R., Method for strengthening air bridge circuits.
  11. Tam Gordon (Chandler AZ) Granick Lisa R. (Philadelphia PA), Method of fabricating airbridge metal interconnects.
  12. Lammert Michael D., Method of forming airbridged metallization for integrated circuit fabrication.
  13. Lammert Michael D. (Manhattan Beach CA), Method of forming airbridged metallization for integrated circuit fabrication.
  14. Zavracky Paul M. (Norwood MA) Morrison ; Jr. Richard H. (Taunton MA), Method of making a micromechanical electric shunt.
  15. Yagi Takayuki,JPX, Method of manufacturing an air bridge type structure for supporting a micro-structure.
  16. Orbach Zvi (Haifa ILX), Personalizable CMOS gate array device and technique.
  17. Williams Ralph E. (Richardson TX), Plated bridge step-over connection for monolithic devices and method for making thereof.
  18. Lewis Robert Lee ; Sebesta Robert David ; Waits Daniel Martin, Process for connecting an electrical device to a circuit substrate.
  19. Carey Charles F. (Endicott NY) Fallon Kenneth M. (Vestal NY) Markovich Voya R. (Endwell NY) Powell Douglas O. (Endicott NY) Vlasak Gary P. (Owego NY) Zarr Richard S. (Apalachin NY), Process for selective application of solder to circuit packages.
  20. Wojnarowski Robert John, Semiconductor interconnect structure for high temperature applications.
  21. Wojnarowski Robert John, Semiconductor interconnect structure for high temperature applications.
  22. Cho, Yeoung-Jun, Semiconductor package.
  23. Moslehi Mehrdad M., Ultra high-speed chip interconnect using free-space dielectrics.
  24. Moslehi Mehrdad M., Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics.
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