초록 ▼

According to the invention, a receive-transmit steerable null antenna processor includes incrementally adjustable delay lines and a variable ratio power network (amplitude balance control) for adjusting the relative phase and amplitude in two or more antenna branches to steer a null on an interferen

According to the invention, a receive-transmit steerable null antenna processor includes incrementally adjustable delay lines and a variable ratio power network (amplitude balance control) for adjusting the relative phase and amplitude in two or more antenna branches to steer a null on an interference source. A digital controller compares a signal which includes a representation of the interference level to a previously sampled value to note improvement or not and adjusts the delay lines and amplitude balance accordingly.

대표청구항 ▼

A steerable null antenna processor system for receiving desired wave energy signals from at least one angular region of space within the area covered by the system and for suppressing interfering signals from at least one other angular region, using antenna means having at least first and second ant

A steerable null antenna processor system for receiving desired wave energy signals from at least one angular region of space within the area covered by the system and for suppressing interfering signals from at least one other angular region, using antenna means having at least first and second antenna elements; said processor system comprising: nulling means coupled between said antenna elements and a common port for supplying said desired wave energy signals to said common port; said nulling means comprising phase means and amplitude means, both the phase means and the amplitude means being adjustable in incremental steps and having control inputs, operative in response to control signals at the control inputs to adjust respectively the phase and amplitude values of the nulling means; the amplitude means being a variable ratio combiner comprised of a quadrature hybrid, a sum-difference hybrid, and two adjustable delay lines between said hybrids; digital controller means having clock means, sample storage means, comparison means, feedback input means, and phase and amplitude memory means having connections to said control inputs of the phase and amplitude means respectively; there being apparatus between said common port and the feedback input means which supplies feedback signals containing a representation of the level of the interfering signal at the common port; the clock means supplying clock signals to provide successive cycles, the comparison means being connected and operative during each cycle to compare a feedback signal from the feedback input means to a previous sample thereof stored in said sample storage means to indicate improvement or no improvement, and to supply said control signals via said memory means to said nulling means to make an appropriate adjustment for steering at least one null to the interfering signals.