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In an Array Processor, a buffering unit including a FIFO buffer and serial-to-parallel converter, is interposed between a control processor and the remainder of the Array Processing circuitry so as to permit the utilization of a vertical instruction set for generating addresses and function numbers

In an Array Processor, a buffering unit including a FIFO buffer and serial-to-parallel converter, is interposed between a control processor and the remainder of the Array Processing circuitry so as to permit the utilization of a vertical instruction set for generating addresses and function numbers which are then serially coupled from the control processor to the buffering unit.

대표청구항 ▼

An Array Processor comprising in combination: a controller having serially generated words as an output therefrom; a buffering unit including a FIFO buffer and a serial-to-parallel converter coupled thereto: means for coupling said serially generated words to said buffering unit; and, a pipelined ar

An Array Processor comprising in combination: a controller having serially generated words as an output therefrom; a buffering unit including a FIFO buffer and a serial-to-parallel converter coupled thereto: means for coupling said serially generated words to said buffering unit; and, a pipelined arithmetic unit and memory coupled to said buffering unit and controlled thereby.