초록 ▼

A circuit for determining each level transition of first and second two logic level input signals and their leading or lagging phase relationship at each level transition and comprising first and second signal level storage means each having first input means responsive to the first and second input

A circuit for determining each level transition of first and second two logic level input signals and their leading or lagging phase relationship at each level transition and comprising first and second signal level storage means each having first input means responsive to the first and second input signals, respectively, first output means, and clock input means and responsive to a clock signal supplied to the clock input means to cause the logic level on its output means to become equal to the logic level on its first input means. First and second Exclusive OR gates each have a first input means connected respectively to said first input means of said first and second signal level storage means, and a second input means connected respectively to said first output means of said first and second signal level storage means. A third Exclusive OR gate responds to equal or non-equal logic levels on said first output terminal of said first Exclusive OR gate and said second input signal to produce first and second logic level, respectively. Additional means respond to the outputs of said first, second, and third Exclusive OR gates to determine the relationship of said first and second input signals at each level transition thereof and to supply a clock signal to the clock input means of said first and second signal level storage means after said additional means determines the phase relationship between said first and second input signals.

대표청구항 ▼

A circuit for determining each level transition of first and second two logic level input signals and their leading or lagging phase relationship at each level transition and comprising: first and second signal level storage means each having first, second and third terminals and responsive to a clo

A circuit for determining each level transition of first and second two logic level input signals and their leading or lagging phase relationship at each level transition and comprising: first and second signal level storage means each having first, second and third terminals and responsive to a clock pulse supplied to its third terminal to cause the signal logic level on its second terminal to become equal to the signal logic level on its first terminal; first and second voltage comparator means each having a first input terminal means connected respectively to said first terminal of said first and second signal level storage means, respectively, and constructed to receive, respectively, said first and second input signals, a second input terminal means connected respectively to said second terminal of said first and second signal logic level storage means, and responsive to equal or non-equal signal logic levels supplied to their first and second input terminal means to produce first and second output signal logic levels, respectively; third voltage comparator means responsive to the equality or non-equality of the signal logic level on said second terminal of said first signal level storage means and said second input signal to produce third and fourth output signal levels, respectively; clock pulse generating means for generating clock pulses; first means responsive to the output signal logic levels of said first, second, and third voltage comparator means to detect each logic level transition of said first and second input signals and the leading or lagging phase relation of said first and second input signals at each logic level transition thereof; and second means for supplying said clock pulses to said third terminal means of said first and second signal level storage means a predetermined time interval after said first means detected said leading or lagging phase relationship of said first and second input signals.