초록 ▼

A phase-locked loop apparatus for deriving clock pulses from return-to-zero data pulses is disclosed. It includes a phase detector for computing the difference, in time, between that portion of a detected data pulse which occurs before a clock pulse edge and the portion after the clock pulse edge. T

A phase-locked loop apparatus for deriving clock pulses from return-to-zero data pulses is disclosed. It includes a phase detector for computing the difference, in time, between that portion of a detected data pulse which occurs before a clock pulse edge and the portion after the clock pulse edge. The difference, once computed, is held for a long period thereafter and is used to drive a voltage controlled oscillator. The voltage controlled oscillator generates the clock pulses which are applied to the phase detector and which comprise the output of the apparatus.

대표청구항 ▼

Apparatus for deriving clock pulses from data pulses, comprising: means for sampling the error in phase between a portion of a data pulse substantially away from the edge thereof and an edge of a corresponding clock pulse, and for holding said error; and a phase locked loop including means for gener

Apparatus for deriving clock pulses from data pulses, comprising: means for sampling the error in phase between a portion of a data pulse substantially away from the edge thereof and an edge of a corresponding clock pulse, and for holding said error; and a phase locked loop including means for generating said clock pulses at a frequency dependent on said held error.