초록 ▼

A separable two dimensional Finite Impulse Response (FIR) digital image processing filter with X-dimension filter section having a delay buffer series to which digitized image signals or pixels are first input. The buffer inputs and output are tapped and pixels tapped off are processed by preset mul

A separable two dimensional Finite Impulse Response (FIR) digital image processing filter with X-dimension filter section having a delay buffer series to which digitized image signals or pixels are first input. The buffer inputs and output are tapped and pixels tapped off are processed by preset multiplier factors and input to an adder where the processed pixels are summed. The summed pixels are fed to a line buffer series of a Y-dimension filter section, tapped off from the filter inputs and output, and processed by further preset multiplier factors. The processed pixels are input to a second adder and summed to provide filtered output pixels. In a second embodiment, the filter is symmetric and has a center point response of unity. In a third embodiment, the filter X and Y dimension filter sections are reversed.

대표청구항 ▼

A two-dimensional finite impulse response filter for filtering image pixels with minimal pixel processing steps, comprising, in combination: first and second sections for filtering image pixels, the output of said first section being input to said second section so that said image pixels are filtere

A two-dimensional finite impulse response filter for filtering image pixels with minimal pixel processing steps, comprising, in combination: first and second sections for filtering image pixels, the output of said first section being input to said second section so that said image pixels are filtered successively to provide filtered pixels at the output of said second section; said first and second sections including: (a) a buffer series for receiving and temporarily storing image pixels to be filtered; (b) adder means for summing discrete pixel inputs to provide a totalized output; (c) pixel buses coupling input/output ports of individual buffers in said buffer series to said adder means whereby to input pixels from buffers in said buffer series to said adder means; and (d) multiplier means in at least one of said pixel buses for multiplying pixels input to said adder means by a predetermined filter factor.