초록 ▼

There is disclosed a balancing network for a piezoresistive semiconductor bridge configuration. The balancing network comprises a plurality of series resistors arranged in series with the sensing elements in the bridge configuration. Each resistor differs from the previous one according to a power o

There is disclosed a balancing network for a piezoresistive semiconductor bridge configuration. The balancing network comprises a plurality of series resistors arranged in series with the sensing elements in the bridge configuration. Each resistor differs from the previous one according to a power of two to form a binary ladder arrangement. The individual resistors are associated with terminals to allow the transducer manufacturer to selectively short one or more resistors to provide zero balance compensation. The resistors are located on the nonactive portion of the semiconductor substrate and are fabricated by the same techniques employed for fabrication of the semiconductor piezoresistive sensing elements to assure temperature tracking of the unit with the desired temperature operating range.

대표청구항 ▼

In an integrated semiconductor transducer arrangement of the type employing a bridge configuration of integrated piezoresistive sensing elements, with said elements deposited on a semiconductor substrate by an integrated circuit technique, the combination therewith of balancing apparatus for providi

In an integrated semiconductor transducer arrangement of the type employing a bridge configuration of integrated piezoresistive sensing elements, with said elements deposited on a semiconductor substrate by an integrated circuit technique, the combination therewith of balancing apparatus for providing a zero shift and balance for said bridge configuration, comprising: a binary resistive ladder comprising a plurality of resistors, each one differing in value from each other by a factor of two and arranged in series with at least one section of said bridge, and means for selectively bypassing desired ones of said resistors according to an output from said transducer upon application thereto of a zero reference pressure, said resistive ladder deposited on said diaphragm according to the same technique as employed for deposition of said piezoresistors.