초록 ▼

A data capture circuit for a logic state analyzer includes a qualifier pattern comparator circuit that responds to a collection of input qualifier signals by producing a number of qualifier pattern signals each representative of the occurrence of a preselectable pattern in the input qualified signal

A data capture circuit for a logic state analyzer includes a qualifier pattern comparator circuit that responds to a collection of input qualifier signals by producing a number of qualifier pattern signals each representative of the occurrence of a preselectable pattern in the input qualified signals. A like number of clock detection circuits each responds separately to the values of separate clock signals by producing separate qualified clock signals, each of the like number of which represents the simultaneous occurrence of a preselected transition in each particular clock signal and of a qualifier pattern signal associated with that clock signal. The several separate qualified clock signals generally occur at separate times, and each is used to individually capture into several temporary storage registers separate collections of data signal values occurring at those separate times. A master clock selection means allows the user to designate as a master clock signal a qualified clock signal that is expected to occur not earlier in sequence than the others. The master clock signal causes transfer of the contents of the temporary storage registers into intermediate storage registers whose outputs are then merged and combined by subsequent and simultaneous forwarding as a single parallel entity to the main data memory of the logic state analyzer, while at the same time the temporary storage registers are freed to capture fresh data.

대표청구항 ▼

A data capture circuit for a logic state analyzer comprising: first and second data signal conditioning means for respective connection to first and second collections of data signals to condition those signals according to preselected thresholds and for respectively producing first and second colle

A data capture circuit for a logic state analyzer comprising: first and second data signal conditioning means for respective connection to first and second collections of data signals to condition those signals according to preselected thresholds and for respectively producing first and second collections of conditioned data signals indicative of the logical values of the signals within the first and second collections of data signals; qualifier signal conditioning means for connection to a collection of qualifier signals to condition those signals according to preselected thresholds and for producing a collection of conditioned qualifier signals indicative of the logical value of the signals within the collection of qualifier signals; first and second clock signal conditioning means for respective connection to first and second clock signals to condition those signals according to preselected thresholds and for respectively producing first and second conditioned clock signals indicative of the logical values of the first and second clock signals; qualifier pattern detection means coupled to the collection of conditioned qualifier signals for producing first and second qualifier pattern signals, each qualifier pattern signal being produced in response to the occurrence of a respective and preselected logical combination of the signals within the collection of conditioned qualifier signals; first and second clock qualification means each respectively coupled to a separate one of the first and second conditioned clock signals and to a separate one of the first and second qualifier pattern signals for respectively producing first and second qualified clock signals, each of which represents the logical conjunction of a conditioned clock signal and an associated qualifier pattern signal; first and second temporary storage means respectively connected to the first and second collections of conditioned data signals and respectively to the first and second qualified clock signals for respectively storing the values of the signals within the first and second collections of conditioned data signals upon the respective occurrence of the first and second qualified clock signals; qualified clock selection means coupled to the first and second qualified clock signals for producing a master clock signal at the conclusion of a delay beginning upon the occurrence of a preselected one of the first and second qualified clock signals; intermediate storage means coupled to receive the contents of the first and second temporary storage means and to the master clock signal for storing the contents of the first and second temporary storage means upon the occurrence of the master clock signal, whereby the first and second temporary storage means are freed to store new data and their combined contents thereafter treated as a single entity; data memory means coupled to receive the contents of the intermediate storage means and to the master clock signal for storing the contents of the intermediate storage means in response to the occurrence of the master clock signal.