$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Integrated circuit package 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/18
출원번호 US-0221103 (1980-12-29)
발명자 / 주소
  • McIver Chandler H. (Tempe AZ)
출원인 / 주소
  • Honeywell Information Systems Inc. (Phoenix AZ 02)
인용정보 피인용 횟수 : 49  인용 특허 : 2

초록

An Integrated Circuit Package in which integrated circuit (I.C.) chips having flexible beam leads, the inner lead bond sites of which are bonded to input/output (I/O) terminals on the active faces of the chips, are mounted active face down on a surface of a substrate. The surface of the substrate is

대표청구항

The combination comprising: an integrated circuit chip having an active face having outer edges, a back face, and a plurality of input/output terminals on the active face; a plurality of flexible beam leads, each lead having an inner and an outer lead bonding site, the inner lead bonding site of eac

이 특허에 인용된 특허 (2)

  1. Hentz Lyle J. (Whitehall PA) Otto Willard G. (Schnecksville PA), Methods for mounting an article on an adherent site on a substrate.
  2. de Miranda William R. R. (Clearwater FL) Smith Edwin R. (Jamestown NC), Tape automated bonding test board.

이 특허를 인용한 특허 (49)

  1. Hodgson Rodney T. (Ossining NY) Jones Harry J. (Austin TX) Ledermann Peter G. (Pleasantville NY) Reiley Timothy C. (Ridgefield CT) Moskowitz Paul A. (Yorktown Heights NY), Balltape structure for tape automated bonding, multilayer packaging, universal chip interconnection and energy beam proc.
  2. Fujii,Takayasu; Sonoda,Isao, Circuit board device and manufacturing method thereof.
  3. Jui-Hsiang Pan TW, Die seal ring.
  4. Bickford Harry R. (57 Sherwood Ave. Ossining NY 10562) Bregman Mark F. (63 Old Washington Rd. Ridgefield CT 06877) Moskowitz Paul A. (R.D. #1 ; Box 343 ; Hunterbrook Rd. Yorktown Heights NY 10598) Pa, Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and pr.
  5. Co, Reynaldo; Leal, Jeffrey S.; Pangrle, Suzette K.; McGrath, Scott; Melcher, De Ann Eileen; Barrie, Keith L.; Villavicencio, Grant; Del Rosario, Elmer M.; Bray, John R., Electrical connector between die pad and z-interconnect for stacked die assemblies.
  6. Co, Reynaldo; Leal, Jeffrey S.; Pangrle, Suzette K.; McGrath, Scott; Melcher, DeAnn Eileen; Barrie, Keith L.; Villavicencio, Grant; del Rosario, Elmer M.; Bray, John R., Electrical connector between die pad and z-interconnect for stacked die assemblies.
  7. Co, Reynaldo; Villavicencio, Grant; Leal, Jeffrey S.; McElrea, Simon J. S., Electrical interconnect for die stacked in zig-zag configuration.
  8. McElrea, Simon J. S.; Andrews, Jr., Lawrence Douglas; McGrath, Scott; Caskey, Terrence; Crane, Scott Jay; Robinson, Marc E.; Cantillep, Loreto, Electrically interconnected stacked die assemblies.
  9. McElrea, Simon J. S.; Andrews, Jr., Lawrence Douglas; McGrath, Scott; Caskey, Terrence; Crane, Scott Jay; Robinson, Marc E.; Cantillep, Loreto, Electrically interconnected stacked die assemblies.
  10. Tao, Min; Sun, Zhuowen; Kim, Hoki; Zohni, Wael; Agrawal, Akash, Enhanced density assembly having microelectronic packages mounted at substantial angle to board.
  11. Katkar, Rajesh; Co, Reynaldo; McGrath, Scott; Prabhu, Ashok S.; Lee, Sangil; Wang, Liang; Shen, Hong, Flipped die stack.
  12. Prabhu, Ashok S.; Katkar, Rajesh; Wang, Liang; Uzoh, Cyprian Emeka, Flipped die stack assemblies with leadframe interconnects.
  13. Delacruz, Javier A.; Haba, Belgacem; Vu, Tu Tam; Katkar, Rajesh, Flipped die stacks with multiple rows of leadframe interconnects.
  14. Delacruz, Javier A.; Haba, Belgacem; Vu, Tu Tam; Katkar, Rajesh, Flipped die stacks with multiple rows of leadframe interconnects.
  15. Davis Earl K. (Tempe AZ) Drye James E. (Mesa AZ) Reed David J. (Mesa AZ), Glass bonding means and method.
  16. Alvarez Juan M. (Medfield MA) Breit Henry F. (Attleboro MA) Levy Steven E. (Plainville MA) Hingorany Premkumar R. (Foxboro MA), Heat dissipating member for mounting a semiconductor device and electrical circuit unit incorporating the member.
  17. Hemler Paul F. (Arnold MD) Rohr William A. (Buffalo NY), Hermetic chip carrier compliant soldering pads.
  18. Ho, Tsz Yin; Merilo, Dioscoro A.; Chow, Seng Guan; Dimaanor, Jr., Antonio B.; Kuan, Heap Hoe, Integrated circuit package in package system.
  19. Chow, Seng Guan; Ying, Ming; Shim, Il Kwon, Integrated circuit package system with die and package combination.
  20. Chow, Seng Guan; Ying, Ming; Shim, Il Kwon, Integrated circuit package system with die and package combination.
  21. Jiang, Tongbi, Method of fabricating tape attachment chip-on-board assemblies.
  22. Tongbi Jiang, Method of fabricating tape attachment chip-on-board assemblies.
  23. Freyman Bruce J. (N. Lauderdale FL) Dorinski Dale (Coral Springs FL) Shurboff John (Coral Springs FL), Method of making an ultra high density pad array chip carrier.
  24. Haba, Belgacem; Sun, Zhuowen; Delacruz, Javier A., Microelectronic packages and assemblies with improved flyby signaling operation.
  25. Carney, Francis J.; Celaya, Phillip; Fauty, Joseph K.; Letterman, James P.; St. Germain, Stephen; Yoder, Jay A., Multi-chip semiconductor connector.
  26. Carney, Francis J.; Celaya, Phillip; Fauty, Joseph K.; Letterman, James P.; St. Germain, Stephen; Yoder, Jay A., Multi-chip semiconductor connector and method.
  27. Smolley Robert (Porteughese Bend CA), Multi-element circuit construction.
  28. Tate Howard L. (Newman Lake WA) Romeike Gary L. (Spokane WA) Tara Vinai M. (Spokane WA) Vocture James L. (Spokane WA), Printed circuit board assembly.
  29. Morley Richard E. (Mason NH) Baker David A. (Mason NH), Printed circuit board heat sink.
  30. Leal, Jeffrey S., Selective die electrical insulation by additive process.
  31. Leal, Jeffrey S., Selective die electrical insulation by additive process.
  32. Webster Harold F. (Scotia NY), Self packaging chip mount.
  33. Sakai Kunito (Amagasaki JPX) Tamaki Akinobu (Amagasaki JPX) Takahama Takashi (Amagasaki JPX), Semiconductor device.
  34. Co, Reynaldo; Melcher, DeAnn Eileen; Pan, Weiping; Villavicencio, Grant, Semiconductor die array structure.
  35. Crane, Scott Jay; McElrea, Simon J. S.; McGrath, Scott; Pan, Weiping; Melcher, De Ann Eileen; Robinson, Marc E., Semiconductor die mount by conformal die coating.
  36. Crane, Scott Jay; McElrea, Simon J. S.; McGrath, Scott; Pan, Weiping; Melcher, De Ann Eileen; Robinson, Marc E., Semiconductor die mount by conformal die coating.
  37. Crane, Scott Jay; McElrea, Simon J. S.; McGrath, Scott; Pan, Weiping; Melcher, DeAnn Eileen; Robinson, Marc E., Semiconductor die mount by conformal die coating.
  38. Watanabe Masayuki (Yokohama JPX) Sugano Toshio (Kokubunji JPX) Tsukui Seiichiro (Komoro JPX) Ono Takashi (Akita JPX) Wakashima Yoshiaki (Kawasaki JPX), Semiconductor integrated circuit device and method of manufacturing the same.
  39. Masayuki Watanabe,JPX ; Toshio Sugano,JPX ; Seiichiro Tsukui,JPX ; Takashi Ono,JPX ; Yoshiaki Wakashima,JPX, Semiconductor memory module having double-sided memory chip layout.
  40. Masayuki, Watanabe; Toshio, Sugano; Seiichiro, Tsukui; Takashi, Ono; Yoshiaki, Wakashima, Semiconductor memory module having double-sided stacked memory chip layout.
  41. Masayuki, Watanabe; Toshio, Sugano; Seiichiro, Tsukui; Takashi, Ono; Yoshiaki, Wakashima, Semiconductor memory module having double-sided stacked memory chip layout.
  42. Watanabe Masayuki JP; Sugano Toshio JP; Tsukui Seiichiro JP; Ono Takashi JP; Wakashima Yoshiaki JP, Semiconductor memory module having double-sided stacked memory chip layout.
  43. McGrath, Scott; Leal, Jeffrey S.; Shenoy, Ravi; Cantillep, Loreto; McElrea, Simon; Pangrle, Suzette K., Stacked die assembly having reduced stress electrical interconnects.
  44. McElrea, Simon J. S.; Robinson, Marc E.; Andrews, Jr., Lawrence Douglas, Support mounted electrically interconnected die assembly.
  45. Jiang,Tongbi, Tape attachment chip-on-board assemblies.
  46. Niki Kenichi (Amagasaki JPX) Kokogawa Toru (Amagasaki JPX) Takasago Hayato (Amagasaki JPX), Tape carrier for assembling an IC chip on a substrate.
  47. Caskey, Terrence; Andrews, Jr., Lawrence Douglas; McGrath, Scott; McElrea, Simon J. S.; Du, Yong; Scott, Mark, Vertical electrical interconnect formed on support prior to die mount.
  48. Prabhu, Ashok S.; Katkar, Rajesh; Moran, Sean, Wafer-level flipped die stacks with leadframes or metal foil interconnects.
  49. Prabhu, Ashok S.; Katkar, Rajesh; Moran, Sean, Wafer-level flipped die stacks with leadframes or metal foil interconnects.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로