초록 ▼

A pulse width modulation comparator having internal latching and resetting functions. The comparator includes a differential input stage having first and second outputs which are connected to supply first and second transistors in a voltage gain stage, respectively. The first output of the input sta

A pulse width modulation comparator having internal latching and resetting functions. The comparator includes a differential input stage having first and second outputs which are connected to supply first and second transistors in a voltage gain stage, respectively. The first output of the input stage drives both of the transistors of the voltage gain stage. The second output of the input stage is connected to drive an output transistor as well as to supply the second transistor of the voltage gain stage. The output of the output transistor is connected via feedback circuitry to drive the transistors of the voltage gain stage. A shunt transistor forms part of the feedback circuit and serves to divert the feedback signal from the voltage gain stage transistors upon the application of a clock reset pulse. An analog voltage is applied to one input of the input stage and a ramp or triangular waveform is applied to the other input. At the point where the ramp exceeds the analog voltage, the voltage gain transistors are turned on and the second output of the input stage goes low, aided by the voltage gain stage. This causes the output transistor to go high, thereby generating positive feedback to drive the voltage gain transistors, thereby latching the output transistor in a high state. At the end of the ramp period, a clock pulse turns on the shunt transistor so as to remove the feedback current from the voltage gain stage and reset the output transistor to a low level.

대표청구항 ▼

1. A comparator circuit having integral latching and resetting, comprising: a differential input stage having first and second sides which are driven by first and second input signals, respectively, whereby when one of said sides is conducting, the other of said sides is not conducting, each of s

1. A comparator circuit having integral latching and resetting, comprising: a differential input stage having first and second sides which are driven by first and second input signals, respectively, whereby when one of said sides is conducting, the other of said sides is not conducting, each of said sides having an output; a voltage gain stage including first and second transistors which are connected to be supplied by said outputs of said first and second sides of said input stage, respectively, said first and second transistors having drive inputs which are connected to be driven by said output of said first side of said input stage; an output stage connected to be driven by said output of said second side of said input stage, said output stage having an output; and a positive feedback network connected from said output of said output stage to provide positive feedback to drive said first and second transistors of said voltage gain stage, said feedback network including circuitry for removing said positive feedback from said first and second transistors upon application of a reset signal. 2. The circuit of claim 1, wherein said positive feedback network includes: a diode connected between said output of said first side of said input stage and said drive inputs of said first and second transistors, said diode isolating said positive feedback from said input stage. 3. The circuit of claim 1 or 2, wherein said circuitry for removing said positive feedback comprises: a shunt transistor supplied by the positive feedback current and driven by said reset signal, the application of said reset signal causing said shunt transistor to conduct the positive feedback current away from said first and second transistors. 4. The circuit of claim 1, wherein said comparator circuit is a pulse width modulation comparator, said first input signal is an analog voltage for which a proportional pulse width signal is desired, said second input signal is a periodic voltage, and said reset signal is a clock signal which is synchronized with said second input signal. 5. The circuit of claim 4, wherein said second input signal is a ramp signal. 6. The circuit of claim 1, wherein each side of said input stage comprises a single transistor. 7. The circuit of claim 6, wherein said transistors in said input stage are of a type which is different from the type of said transistors in said voltage gain stage. 8. A pulse width modulation comparator for comparing an analog voltage with a periodic voltage, comprising: a differential input stage including first and second sides, each side including a transistor connected to a supply current, said transistor on said first side being driven by said analog voltage and said transistor on said second side being driven by said periodic voltage, each of said sides having an output; a voltage gain stage including a first transistor supplied by said output of said transistor of said first side of said input stage and a second transistor supplied by said output of said second side of said input stage, said first and second transistors having drive inputs which are driven by said output of said first side of said input stage; an output stage connected to said output of said second side of said input stage, said output stage having an output; and a positive feedback network including a resistor connected to supply positive feedback current from said output of said output stage to said drive inputs of said first and second transistors, a diode connected between said output of said first side of said input stage and said drive inputs of said first and second transistors, said diode isolating said feedback current from said input stage, and a shunt transistor having a supply input connected to said resistor and a drive input connected to a clock voltage which is synchronized with said periodic voltage, whereby when said periodic voltage exceeds said analog voltage, said first and second transistors will initially be turned on by said output of said first side of said input stage, thereby causing said output of said output stage to go high and drive said first and second transistors through said resistor, and wherein a clock pulse subsequently causes said shunt transistor to conduct and divert said positive feedback current away from said first and second transistors to thereby reset said comparator. 9. The comparator of claim 8, wherein said periodic voltage is a ramp voltage. 10. The comparator of claim 9, wherein said periodic voltage is a triangle voltage. 11. The comparator of claim 8, wherein said transistors in said input stage are of a type which is different from the type of said transistors in said voltage gain stage. 12. The comparator of claim 1 or 8, further including: an output buffer stage connected to said output of said output stage. 13. A pulse width modulation comparator providing latching and resetting functions, comprising: a differential input stage having an analog voltage as a first input and a periodic voltage as a second input, said input stage having first and second outputs, wherein the value of said outputs is a function of the difference between said analog voltage and said periodic voltage; first and second transistors connected to be supplied by said first and second outputs, respectively, said first and second transistors having drive inputs which are connected to be driven by said first output, the turning on of said transistors aiding in the switching of said second output from a high level to a low level; an output stage driven by said second output, said output stage having an output; and a positive feedback circuit for providing a positive feedback drive current from said output of said output stage to said drive inputs of said transistors, said feedback current latching said output of said output stage, said feedback circuit including circuitry for selectively removing said feedback current from said transistors. 14. The comparator of claim 13, wherein said circuitry for removing includes a shunt transistor which is turned on to shunt feedback current away from said transistors and wherein said shunt transistor is driven by a clock signal which is synchronized with said periodic voltage.