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Process for making multilayer integrated circuit substrate 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B05D-005/12
출원번호 US-0334297 (1981-12-24)
발명자 / 주소
  • Nair Krishna K. (Binghamton NY) Snyder Keith A. (Vestal NY)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 58  인용 특허 : 1

초록

A process is provided for making a multilayer integrated circuit substrate having improved via connection. A first layer M1 of chrome-copper-chrome is applied to a ceramic substrate and the circuits etched. A polyimide layer is then applied, cured, and developed and etched to provide via holes in th

대표청구항

A process for making a multilayer integrated circuit substrate having via connections which comprises: depositing a first layer of chrome-copper-chrome onto an inorganic substrate; photoetching circuitry on said first layer; applying a layer of polyimide; photoetching via holes in the polyimide down

이 특허에 인용된 특허 (1)

  1. Fraser David Bruce (Berkeley Heights NJ), Sputter coating with charged particle flux control.

이 특허를 인용한 특허 (58)

  1. Adamopoulos Eleftherios (Bronx NY) Kim Jungihl (Seoul KRX) Lee Kang-Wook (Yorktown Heights NY) Oh Tae S. (Seoul KRX) O\Toole Terrence R. (Hopewell Junction NY) Purushothaman Sampath (Yorktown Heights, Adhesive layer in multi-level packaging and organic material as a metal diffusion barrier.
  2. Farrar Paul A., Copper metallurgy in integrated circuits.
  3. Farrar, Paul A., Copper metallurgy in integrated circuits.
  4. Farrar,Paul A., Electronic apparatus having a core conductive structure within an insulating layer.
  5. Jones Alan L. (Endwell NY) Synder Keith A. (Vestal NY), Electronic package with a device positioned above a substrate by suction force between the device and heat sink.
  6. Ho Paul S. C. (Chappaqua NY) Hahn Peter O. (Burghausen NY DEX) Lefakis Harry (Shrub Oak NY) Rubloff Gary W. (Katonah NY), Enhanced adhesion between metals and polymers.
  7. Clementi Robert J. (Binghamton NY) Gazdik Charles E. (Endicott NY) Lafer William (Chenango Bridge NY) Lovesky Roy L. (Vestal NY) McBride Donald G. (Binghamton NY) Munson Joel V. (Port Crane NY) Skarv, Flexible film semiconductor chip carrier.
  8. Farrar Paul A., Forming submicron integrated-circuit wiring from gold, silver, copper and other metals.
  9. Farrar Paul A., Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals.
  10. Farrar, Paul A., Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals.
  11. Gazdik Charles E. (Endicott NY) McBride Donald G. (Binghamton NY) Seraphim Donald P. (Vestal NY) Toole Patrick A. (Westport CT), Full panel electronic packaging structure.
  12. Sedberry Donald C. (Gwynedd PA), High-density circuit and method of its manufacture.
  13. Sedberry Donald C. (Gwynedd PA), High-density circuit and method of its manufacture.
  14. Volfson David (Worcester MA) Senturia Stephen D. (Boston MA), High-density, multi-level interconnects, flex circuits, and tape for TAB.
  15. Farrar,Paul A., Hplasma treatment.
  16. Farrar, Paul A., Integrated circuit and seed layers.
  17. Farrar,Paul A., Integrated circuit and seed layers.
  18. Farrar,Paul A., Integrated circuit and seed layers.
  19. Gansauge Peter (Boeblingen DEX) Kreuter Volker (Schoenaich DEX) Schettler Helmut (Dettenhausen DEX), Integrated circuit substrate with contacts thereon for a packaging structure.
  20. Farrar Paul A., Integrated circuit with oxidation-resistant polymeric layer.
  21. Farrar, Paul A., Mask on a polymer having an opening width less than that of the opening in the polymer.
  22. Chiang Chien ; Fraser David B., Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections.
  23. Chiang Chien ; Fraser David B., Method for forming multileves interconnections for semiconductor fabrication.
  24. Jones Carol R. (Binghamton NY) Susko Robin A. (Owego NY), Method for laminating organic materials via surface modification.
  25. Ahn,Kie Y.; Forbes,Leonard, Method for making integrated circuits.
  26. Dubin, Valery, Method for making interconnects and diffusion barriers in integrated circuits.
  27. Geldermans Pieter (Poughkeepsie NY) Mathad Gangadhara S. (Poughkeepsie NY), Method of fabricating a chip interposer.
  28. Gurol Ismail M. (Seattle WA), Method of making molded circuit board.
  29. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  30. Ahn,Kie Y.; Forbes,Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  31. Ahn Kie Y. ; Forbes Leonard, Methods for making copper and other metal interconnections in integrated circuits.
  32. Ahn,Kie Y.; Forbes,Leonard, Methods for making copper and other metal interconnections in integrated circuits.
  33. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  34. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  35. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.
  36. Valery Dubin, Methods for making interconnects and diffusion barriers in integrated circuits.
  37. Mu Xiao-Chun (Saratoga CA) Sivaram Srinivasan (San Jose CA) Gardner Donald S. (Mountain View CA) Fraser David B. (Danville CA), Methods of forming an interconnect on a semiconductor substrate.
  38. Ahn,Kie Y.; Forbes,Leonard; Eldridge,Jerome M., Multilevel copper interconnect with double passivation.
  39. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.
  40. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.
  41. Zupancic Joseph J. (Bensenville IL), Photodefinable interlevel dielectrics.
  42. Acosta Raul E. (White Plains NY) Horkans Wilma J. (Ossining NY) Mukherjee Ruby (San Jose CA) Olsen Judith D. (Goldens Bridge NY), Prevention of mechanical and electronic failures in heat-treated structures.
  43. Tokunaga Takafumi (Tokorozawa JPX) Tsuneoka Masatoshi (Ohme JPX) Mizukami Koichiro (Akishima JPX), Process for producing semiconductor integrated circuit device having copper interconnections and/or wirings, and device.
  44. Joshi Rajiv V. ; Cuomo Jerome J. ; Dalal Hormazdyar M. ; Hsu Louis L., Refractory metal capped low resistivity metal conductor lines and vias.
  45. Joshi Rajiv V. ; Cuomo Jerome J. ; Dalal Hormazdyar M. ; Hsu Louis L., Refractory metal capped low resistivity metal conductor lines and vias.
  46. Joshi Rajiv V. ; Cuomo Jerome J. ; Dalal Hormazdyar M. ; Hsu Louis L., Refractory metal capped low resistivity metal conductor lines and vias.
  47. Joshi Rajiv V. ; Cuomo Jerome J. ; Dalal Hormazdyar M. ; Hsu Louis L., Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD.
  48. Boss David W. (Beacon NY) Carr Timothy W. (Hopewell Junction NY) Dubetsky Derry J. (Wappingers Falls NY) Greenstein George M. (Hopewell Junction NY) Grobman Warren D. (Carmel NY) Hayunga Carl P. (Pou, Sealing and stress relief layers and use thereof.
  49. Ahn,Kie Y.; Forbes,Leonard, Selective electroless-plated copper metallization.
  50. Bakos Peter (Austin TX) Darrow Russell E. (Endicott NY) Franchak Nelson P. (Binghamton NY) Funari Joseph (Vestal NY), Structure containing a layer consisting of a polyimide and an organic filled and method for producing such a structure.
  51. Farrar, Paul A., Structures and methods to enhance copper metallization.
  52. Farrar, Paul A., Structures and methods to enhance copper metallization.
  53. Farrar, Paul A., Structures and methods to enhance copper metallization.
  54. Farrar,Paul A., Structures and methods to enhance copper metallization.
  55. Farrar,Paul A., Structures and methods to enhance copper metallization.
  56. Cyril Cabral, Jr. ; Patrick William Dehaven ; Daniel Charles Edelstein ; David Peter Klaus ; James Manley Pollard, III ; Carol L. Stanis ; Cyprian Emeka Uzoh, Thin film metal barrier for electrical interconnections.
  57. Anschel Morris (Wappingers Falls NY) Ormond Douglas W. (Wappingers Falls NY) Hayunga Carl P. (Poughkeepsie NY), Thin film metallization process for improved metal to substrate adhesion.
  58. Yorikane, Masaharu; Ohseki, Noboru, Titanium coated aluminum leads.
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