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Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-001/14
출원번호 US-0244854 (1981-03-18)
발명자 / 주소
  • Anthony Thomas R. (Schenectady NY)
출원인 / 주소
  • General Electric Company (Schenectady NY 02)
인용정보 피인용 횟수 : 178  인용 특허 : 2

초록

Alignment-enhancing electrically conductive feed-through paths are provided for the high-speed low-loss transfer of electrical signals between integrated circuits of a plurality of silicon-on-sapphire bodies arrayed in a stack. The alignment-enhancing feed-throughs are made by a process involving th

대표청구항

An article of manufacture comprising in combination: (a) a plurality of bodies, said bodies being disposed in an array, each said body being adjacent to a next body with a relatively uniform gap therebetween, each said body having top and bottom major opposed surfaces substantially parallel to each

이 특허에 인용된 특허 (2)

  1. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  2. Tracy ; John M., Method of fabricating an array of flexible metallic interconnects for coupling microelectronics components.

이 특허를 인용한 특허 (178)

  1. Lin, Chu-Fu; Kuo, Chien-Li; Yang, Ching-Li, Anti-fuse structure and programming method thereof.
  2. Moshayedi Mark, Apparatus for stacking semiconductor chips.
  3. Wood,Alan G.; Hiatt,William M.; Hembree,David R., Backside method for fabricating semiconductor components with conductive interconnects.
  4. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Backside warpage control structure and fabrication method.
  5. Oh Sung Ho,KRX, Ball grid array semiconductor package and method of fabricating the same.
  6. Forbes, Leonard, Capacitive techniques to reduce noise in high speed interconnections.
  7. Forbes,Leonard, Capacitive techniques to reduce noise in high speed interconnections.
  8. Lin, Yung-Chang; Kuo, Chien-Li, Capacitor structure and method of forming the same.
  9. Hsiao, Wei-Min, Carrier bonding and detaching processes for a semiconductor wafer.
  10. Yang, Kuo-Pin; Hsiao, Wei-Min; Hung, Cheng-Hui, Carrier bonding and detaching processes for a semiconductor wafer.
  11. Panicker Ramachandra M. P. (Camarillo CA) Agarwal Anil K. (Poway CA), Ceramic substrate with metal filled via holes for hybrid microcircuits and method of making the same.
  12. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Coaxial integrated circuitry interconnect lines, and integrated circuitry.
  13. Ahn, Kie Y.; Forbes, Leonard; Cloud, Eugene H., Compact system module with built-in thermoelectric cooling.
  14. Ahn,Kie Y.; Forbes,Leonard; Cloud,Eugene H., Compact system module with built-in thermoelectric cooling.
  15. Ahn Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.
  16. Ahn, Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.
  17. Ahn, Kie Y., Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry.
  18. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode.
  19. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode semiconductor device.
  20. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode semiconductor device.
  21. Uka,Harshad K, Connection for flex circuit and rigid circuit board.
  22. James Douglas Wehrly, Jr., Contact member stacking system and method.
  23. Wehrly, Jr., James Douglas, Contact member stacking system and method.
  24. Forbes, Leonard; Ahn, Kie Y., Current mode signal interconnects and CMOS amplifier.
  25. Siniaguine, Oleg, Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture.
  26. Mizoguchi, Masanori, Electrical connection structure.
  27. Lindeman Richard J. (Wood Dale IL), Electrical connectors.
  28. Armezzani, Gregg J.; Heller, Matthew A., Electronic package with stacked connections and method for making same.
  29. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Embedded component package and fabrication method.
  30. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Embedded component package and fabrication method.
  31. Day, John K.; Ruben, David A.; Sandlin, Michael S., Embedded metallic structures in glass.
  32. Lin, Chin-Fu; Wu, Chun-Yuan; Liu, Chih-Chien; Tsai, Teng-Chun; Chien, Chin-Cheng, Fabrication method and structure of through silicon via.
  33. Burns,Carmen D.; Roper,David; Cady,James W., Flexible circuit connector for stacked chip module.
  34. Belgacem Haba, Forming microelectronic connection components by electrophoretic deposition.
  35. Burns, Carmen D., High density integrated circuit module.
  36. Gaynes Michael Anthony ; Emerick Alan James ; Puligandla Viswanadham ; Woychik Charles Gerard ; Zalesinski Jerzy Maria, High density integrated circuit packaging with chip stacking and via interconnections.
  37. Gaynes Michael Anthony ; Emerick Alan James ; Puligandla Viswanadham ; Woychik Charles Gerard ; Zalesinski Jerzy Maria, High density integrated circuit packaging with chip stacking and via interconnections.
  38. Gaynes Michael Anthony ; Emerick Alan James ; Puligandla Viswanadham ; Woychik Charles Gerard ; Zalesinski Jerzy Maria, High density integrated circuit packaging with chip stacking and via interconnections.
  39. Kie Y. Ahn ; Leonard Forbes ; Paul Farrar, High performance packaging for microprocessors and DRAM chips which minimizes timing skews.
  40. Forbes, Leonard; Ahn, Kie Y.; Akram, Salman, High permeability layered films to reduce noise in high speed interconnects.
  41. Forbes,Leonard; Ahn,Kie Y.; Akram,Salman, High permeability layered films to reduce noise in high speed interconnects.
  42. Swan, Johanna M.; Mahajan, Ravi V.; Natarajan, Bala, Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme.
  43. Swan, Johanna M.; Natarajan, Bala; Chiang, Chien; Atwood, Greg; Rao, Valluri R., Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme.
  44. Swan,Johanna M.; Natarajan,Bala; Chiang,Chien; Atwood,Greg; Rao,Valluri R., Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme.
  45. Siniaguine, Oleg, Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate.
  46. Ahn Kie Y., Integrated circuitry and methods of forming integrated circuitry.
  47. Kie Y. Ahn, Integrated circuitry having conductive passageway interconnecting circuitry on front and back surfaces of a wafer fragment.
  48. Oleg Siniaguine, Integrated circuits and methods for their fabrication.
  49. Siniaguine Oleg, Integrated circuits and methods for their fabrication.
  50. Siniaguine, Oleg, Integrated circuits and methods for their fabrication.
  51. Siniaguine, Oleg, Integrated circuits and methods for their fabrication.
  52. Siniaguine, Oleg, Integrated circuits and methods for their fabrication.
  53. Fuentes, Ruben; Dunlap, Brett, Integrated passive device structure and method.
  54. Chen, Chun-Hung; Lin, Ming-Tse; Lin, Yung-Chang; Kuo, Chien-Li, Integrated structure and method for fabricating the same.
  55. Bohr, Mark T., Interposer and method of making same.
  56. Bohr,Mark T., Interposer and method of making same.
  57. Kuo, Chien-Li, Interposer structure and manufacturing method thereof.
  58. Carlson, Richard O.; Glascock, II, Homer H.; Loughran, James A.; Webster, Harold F., Low loss, multilevel silicon circuit board.
  59. Kolics, Artur; Redeker, Fritz, Metallization mixtures and electronic devices.
  60. Kolics, Artur; Redeker, Fritz, Metallization processes, mixtures, and electronic devices.
  61. Hua, Pei Hsing; Chang, Hui-Shan, Method for dicing a semiconductor wafer having through silicon vias and resultant structures.
  62. Hembree, David R; Wood, Alan G., Method for fabricating a through wire interconnect (TWI) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer.
  63. Hembree, David R.; Wood, Alan G., Method for fabricating semiconductor component having encapsulated through wire interconnect (TWI).
  64. Hembree,David R., Method for fabricating semiconductor components with through wire interconnects.
  65. Hembree, David R., Method for fabricating stacked semiconductor components with through wire interconnects.
  66. Hembree, David R.; Wood, Alan G., Method for fabricating stacked semiconductor system with encapsulated through wire interconnects (TWI).
  67. Lu, Yen-Liang; Lin, Chun-Ling; Hsu, Chi-Mao; Lin, Chin-Fu; Chen, Chun-Hung; Cheng, Tsun-Min; Tsai, Meng-Hong, Method for fabricating through-silicon via structure.
  68. Brian Eugene Curcio ; Peter Alfred Gruber ; Frederic Maurer ; Konstantinos I. Papathomas ; Mark David Poliks, Method for filling high aspect ratio via holes in electronic substrates and the resulting holes.
  69. Kuo, Chien-Li; Lin, Yung-Chang, Method for forming semiconductor device with through silicon via.
  70. Yang, Ching-Li; Kuo, Chien-Li; Chiang, Chung-Sung; Tsai, Yu-Han; Kang, Chun-Wei, Method for forming semiconductor structure having through silicon via for signal and shielding structure.
  71. Soh, Hyongsok, Method for interconnecting arrays of micromechanical devices.
  72. Xu Zheng ; Forster John ; Yao Tse-Yong, Method for low thermal budget metal filling and planarization of contacts vias and trenches.
  73. Halahan, Patrick B., Method for manufacturing a structure comprising a substrate with a cavity and a semiconductor integrated circuit bonded to a contact pad located in the cavity.
  74. Tsao, Wei-Che; Hsu, Chia-Lin; Lin, Jen-Chieh; Tsai, Teng-Chun; Hsu, Hsin-Kuo; Hsieh, Ya-Hsueh; Huang, Ren-Peng; Chen, Chih-Hsien; Lin, Wen-Chin; Hsieh, Yung-Lun, Method for manufacturing through-silicon via.
  75. Liu, Hung-Ming, Method for testing through-silicon-via (TSV) structures.
  76. Zhang, Jian-Jun; Fang, Han-Chuan; Shu, Xiao-Wei; Zhang, Jian-Dong; Liu, Yan-Jun; Zhang, Miao, Method of fabricating isolation structure.
  77. Wood, Alan G.; Farnworth, Warren M.; Hembree, David R., Method of fabricating semiconductor components with through interconnects.
  78. Bohr, Mark T., Method of making an interposer.
  79. Chen, Hsin-Yu; Tsai, Yu-Han; Lin, Chun-Ling; Yang, Ching-Li; Cheng, Home-Been, Method of manufacturing semiconductor structure.
  80. Suh,Min Suk; Kim,Sung Min, Method of manufacturing wafer level stack package.
  81. Wood, Alan G.; Hembree, David R., Methods and systems for fabricating semiconductor components with through wire interconnects (TWI).
  82. Wood, Alan G.; Hiatt, William M.; Hembree, David R., Methods for fabricating semiconductor components with conductive interconnects.
  83. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Methods of forming coaxial integrated circuitry interconnect lines.
  84. Haba, Belgacem, Methods of forming semiconductor stacked die devices.
  85. Haba, Belgacem, Microelectronic connection components utilizing conductive cores and polymeric coatings.
  86. Matsumoto Masaru (Yamato JPX) Nishihara Mikio (Tokyo JPX) Kuwabara Kiyoshi (Yokohama JPX), Multilayer printed wiring board.
  87. Chen, Kuo-Hua, Neural sensing device and method for making the same.
  88. Chen, Kuo-Hua; Chang, Chih-Wei; Chiou, Jin-Chern, Neural sensing device and method for making the same.
  89. Imaoka,Norio, Optical device, optical module, semiconductor apparatus and its manufacturing method, and electronic apparatus.
  90. Siniaguine Oleg ; Savastiouk Sergey, Package of integrated circuits and vertical integration.
  91. Shen, Chi-Chih; Chen, Jen-Chuan; Pan, Tommy; Chang, Hui-Shan; Hung, Chia-Lin, Package structure and package process.
  92. Kuo, Chien-Li; Lin, Yung-Chang; Lin, Ming-Tse, Package structure having silicon through vias connected to ground potential.
  93. Carlson Randolph S. (Carson City NV), Packaging system for stacking integrated circuits.
  94. Carlson Randolph S. (Carson City NV) Chase Charles P. (Carson City NV), Packaging system for stacking integrated circuits.
  95. Anderson James C., Pin array set-up device.
  96. Kano Ryuichi,JPX, Polyhedral IC package for making three dimensionally expandable assemblies.
  97. Wood, Alan G.; Hembree, David R., Semiconductor component having through wire interconnect (TWI) with compressed wire.
  98. Hembree, David R., Semiconductor component having through wire interconnect with compressed bump.
  99. Hembree, David R.; Wood, Alan G., Semiconductor components having encapsulated through wire interconnects (TWI).
  100. Wood, Alan G.; Farnworth, Warren M.; Hembree, David R., Semiconductor components having through interconnects.
  101. Wood,Alan G.; Hembree,David R., Semiconductor components having through wire interconnects (TWI).
  102. Hembree, David R., Semiconductor components with through wire interconnects.
  103. Kuo, Chien-Li; Lin, Yung-Chang, Semiconductor device.
  104. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device and manufacturing method thereof.
  105. Hsu, Chih-Jing; Ou, Ying-Te; Fu, Chieh-Chen; Huang, Che-Hau, Semiconductor device and method for manufacturing the same.
  106. Do, Won Chul; Ko, Yong Jae, Semiconductor device comprising a conductive pad on a protruding-through electrode.
  107. Chen, Yung-Jen; Ding, Yi-Chuan; Huang, Min-Lung, Semiconductor device having conductive via and manufacturing process.
  108. Chen, Yung-Jen; Ding, Yi-Chuan; Huang, Min-Lung, Semiconductor device having conductive via and manufacturing process for same.
  109. Chen, Kuo Hua; Tsai, Li Wen, Semiconductor device having conductive vias and semiconductor package having semiconductor device.
  110. Cheng, Hung-Hsiang; Lin, Tzu-Chih; Hung, Chang-Ying; Wu, Chih-Wei, Semiconductor device having shielded conductive vias.
  111. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device having through electrodes protruding from dielectric layer.
  112. Kuo, Chien-Li; Lin, Yung-Chang; Lin, Ming-Tse; Wu, Kuei-Sheng; Lin, Chia-Fang, Semiconductor device having through silicon trench shielding structure surrounding RF circuit.
  113. Huang, Che-Hau; Ou, Ying-Te, Semiconductor device with conductive vias.
  114. Yoo, Min; Lee, Ki Wook; Lee, Min Jae, Semiconductor devices and fabrication methods thereof.
  115. Wang, Meng-Jen, Semiconductor element having conductive vias and semiconductor package having a semiconductor element with conductive vias and method for making the same.
  116. Hembree, David R; Wood, Alan G., Semiconductor module system having encapsulated through wire interconnect (TWI).
  117. Hembree, David R.; Wood, Alan G., Semiconductor module system having stacked components with encapsulated through wire interconnects (TWI).
  118. Yen, Han-Chee; Chen, Shih-Yuan; Lai, Chien-Pai; Cheng, Ming-Hsien, Semiconductor package having a waveguide antenna and manufacturing method thereof.
  119. Lin, I-Chia; Jou, Sheng-Jian; Yen, Han-Chee, Semiconductor package having an antenna and manufacturing method thereof.
  120. Park, Sung Su; Kim, Jin Young; Jin, Jeong Gi, Semiconductor package having through holes.
  121. Liao, Kuo-Hsien; Chan, Chi-Hong; Fuyu, Shih, Semiconductor package integrated with conformal shield and antenna.
  122. Yen, Han-Chee; Chung, Chi-Sheng; Liao, Kuo-Hsien; Yeh, Yung-I, Semiconductor package integrated with conformal shield and antenna.
  123. Hung, Chia-Lin; Chen, Jen-Chuan; Chang, Hui-Shan; Yang, Kuo-Pin, Semiconductor package with through silicon vias and method for making the same.
  124. Haba, Belgacem, Semiconductor stacked die devices.
  125. Haba,Belgacem, Semiconductor stacked die devices and methods of forming semiconductor stacked die devices.
  126. Chen, Chun-Hung; Lin, Ming-Tse; Kuo, Chien-Li; Wu, Kuei-Sheng, Semiconductor structure.
  127. Li, Tzung-Lin; Wu, Chun-Chang; Tseng, Chih-Yu, Semiconductor structure and method for reducing noise therein.
  128. Wang, Meng-Jen, Semiconductor structure having conductive vias and method for manufacturing the same.
  129. Chen, Chien-Hua; Lee, Teck-Chong; Shih, Hsu-Chiang; Hsieh, Meng-Wei, Semiconductor structure with passive element network and manufacturing method thereof.
  130. Clements Ken (Santa Cruz CA), Semiconductor wafer array.
  131. Clements Ken (Santa Cruz CA), Semiconductor wafer array with electrically conductive compliant material.
  132. Wang, Yung-Hui, Semiconductor wafer, semiconductor process and semiconductor package.
  133. Ahn, Kie Y.; Forbes, Leonard, Silicon interposer with optical connections.
  134. Kie Y. Ahn ; Leonard Forbes, Silicon interposer with optical connections.
  135. Ahn Kie Y. ; Forbes Leonard, Stacked integrated circuits.
  136. Ahn Kie Y. ; Forbes Leonard, Stacked integrated circuits.
  137. Kie Y. Ahn ; Leonard Forbes, Stacked integrated circuits.
  138. Jeong,Se Young; Lee,Kang Wook, Stacked multi-chip semiconductor package improving connection reliability of stacked chips.
  139. Wood, Alan G.; Hembree, David R., Stacked semiconductor component having through wire interconnect (TWI) with compressed wire.
  140. Wood, Alan G.; Hiatt, William M.; Hembree, David R., Stacked semiconductor components having conductive interconnects.
  141. Wood, Alan G.; Hembree, David R., Stacked semiconductor components with through wire interconnects (TWI).
  142. Ishino, Masakzau; Ikeda, Hiroaki; Yamada, Junji, Stacked semiconductor device.
  143. Meadows,Paul Milton, Stacking circuit elements.
  144. Burns, Carmen D.; Wilder, James G.; Dowden, Julian, Stacking system and method.
  145. Ahn Kie Y. ; Forbes Leonard ; Cloud Eugene H., Structure and method for a high performance electronic packaging assembly.
  146. Ahn, Kie Y.; Forbes, Leonard; Cloud, Eugene H., Structure and method for a high-performance electronic packaging assembly.
  147. Geusic Joseph E. ; Forbes Leonard ; Ahn Kie Y., Structure and method for an electronic assembly.
  148. Joseph E. Geusic ; Leonard Forbes ; Kie Y. Ahn, Structure and method for an electronic assembly.
  149. Halahan, Patrick B., Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity.
  150. Volfovski, Leon; Kulkarni, Mayur G., Substrate support with feedthrough structure.
  151. Lin, Chu-Fu; Lin, Ming-Tse; Lin, Yung-Chang, Substrate with integrated passive devices and method of manufacturing the same.
  152. Rangsten, Pelle; Johansson, Hakan; Bejhed, Johan, Substrate-penetrating electrical connections.
  153. Wood, Alan G.; Hiatt, William M.; Hembree, David R., System for fabricating semiconductor components with conductive interconnects.
  154. Hembree, David R., System for fabricating semiconductor components with through wire interconnects.
  155. Hembree, David R.; Wood, Alan G., System with semiconductor components having encapsulated through wire interconnects (TWI).
  156. Dunn, Jr., Richard Anthony, Systems and methods for scalable parallel data processing and process control.
  157. Oleg Siniaguine ; Patrick B. Halahan ; Sergey Savastiouk, Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners.
  158. Huang, Min Lung; Wang, Wei Chung; Cheng, Po Jen; Yee, Kuo Chung; Su, Ching Huei; Lo, Jian Wen; Lin, Chian Chi, Three-dimensional package and method of making the same.
  159. Huang, Min-Lung; Wang, Wei-Chung; Cheng, Po-Jen; Yee, Kuo-Chung; Su, Ching-Huei; Lo, Jian-Wen; Lin, Chian-Chi, Three-dimensional package and method of making the same.
  160. Huang,Min Lung; Wang,Wei Chung; Cheng,Po Jen; Yee,Kuo Chung; Su,Ching Huei; Lo,Jian Wen; Lin,Chian Chi, Three-dimensional package and method of making the same.
  161. Huang, Kuo-Hsiung; Chiou, Chun-Mao; Chen, Hsin-Yu; Tsai, Yu-Han; Yang, Ching-Li; Cheng, Home-Been, Through silicon via and method of forming the same.
  162. Huang, Kuo-Hsiung; Chiou, Chun-Mao; Chen, Hsin-Yu; Tsai, Yu-Han; Yang, Ching-Li; Cheng, Home-Been, Through silicon via and method of forming the same.
  163. Kuo, Chien-Li; Chen, Chun-Hung; Lin, Ming-Tse; Lin, Yung-Chang, Through silicon via and process thereof.
  164. Chen, Hsin-Yu; Cheng, Home-Been; Tsai, Yu-Han; Yang, Ching-Li, Through silicon via structure.
  165. Chen, Hsin-Yu; Cheng, Home-Been; Tsai, Yu-Han; Yang, Ching-Li, Through silicon via structure and method of fabricating the same.
  166. Wang, Chen-Chao; Ou, Ying-Te, Through silicon vias for semiconductor devices and manufacturing method thereof.
  167. Wang, Chen-Chao; Ou, Ying-Te, Through silicon vias for semiconductor devices and manufacturing method thereof.
  168. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  169. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  170. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
  171. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
  172. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  173. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  174. Wood, Alan G; Hembree, David R, Through wire interconnect (TWI) for semiconductor components having wire in via and bonded connection with substrate contact.
  175. Hembree, David R.; Wood, Alan G., Through wire interconnect (TWI) having bonded connection and encapsulating polymer layer.
  176. Tsai, Teng-Chun; Wu, Chun-Yuan; Lin, Chin-Fu; Liu, Chih-Chien; Chien, Chin-Cheng, Through-silicon via forming method.
  177. Forbes, Leonard; Cloud, Eugene H.; Ahn, Kie Y., Transmission lines for CMOS integrated circuits.
  178. Forbes, Leonard; Cloud, Eugene H.; Ahn, Kie Y., Transmission lines for CMOS integrated circuits.
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