IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0331718
(1981-12-17)
|
우선권정보 |
FR-0027871 (1980-12-31) |
발명자
/ 주소 |
- Periot Jean-Marie (Isle d\Espagnac FRX)
|
출원인 / 주소 |
- La Telemecanique Electrique (FRX 03)
|
인용정보 |
피인용 횟수 :
5 인용 특허 :
1 |
초록
▼
A detector apparatus of the two-terminal type supplied with rectified A.C. power (e1, e2, v1 v2, D7-D10) the voltage of which can vary in a wide range, for controlling a series-connected load (CH), including at least one thyristor (TH1) and a Zener diode (Z3), a detector-control circuit assembly (CA
A detector apparatus of the two-terminal type supplied with rectified A.C. power (e1, e2, v1 v2, D7-D10) the voltage of which can vary in a wide range, for controlling a series-connected load (CH), including at least one thyristor (TH1) and a Zener diode (Z3), a detector-control circuit assembly (CAP) associated with the load, the output (s) of which biases the base of a first transistor (T1), a capacitor (C5) serving as a power supply for the detector control circuit (CAP), and means for protection against overloads, which include a MOS-type transistor (T3), a second transistor (T2) connected to the grid of said MOS transistor, and a differential amplifier (A) connected in series with the base of said first transistor (T1).
대표청구항
▼
A detector apparatus for controlling the flow of current through a load in dependence with information provided by a sensor, said detector apparatus comprising: (i) signal generating means (CAP) for generating an output signal from the said information, said signal generating means having first (b1)
A detector apparatus for controlling the flow of current through a load in dependence with information provided by a sensor, said detector apparatus comprising: (i) signal generating means (CAP) for generating an output signal from the said information, said signal generating means having first (b1) and second (b2) power supply inputs and a signal output (s); (ii) first and second power supply terminals (e1e2), the detector apparatus having first and second terminals, the first terminal of the apparatus being connected to the first power supply terminal (e1) through the load and the second terminal of the apparatus being connected to the second power supply terminal (e2); (iii) rectifier means (D7-D10) having a pair of input terminals connected accross the first and second terminals of the apparatus and a pair of output terminals and first (VDD) and second (VSS) power supply lines connecting the respective output terminals of the rectifier means to the respective power supply inputs (b1b2) of the signal generating means; (iv) a high gain solid state component (T3) having a source (S), a drain (D) and a gate (G), said drain being connected to the first power supply line (VDD) and said gate being connected to the first power supply (VDD) of the rectifier means through a biasing resistor (R13); (v) circuit means, including a first thyristor (TH1) having a gate and a Zener diode (Z3) connected in series and in opposition, said circuit means connecting the source (S) of the said high gain solid state component (T3) to the second power supply line (VSS), said Zener diode (Z3) having an anode and a cathode; (vi) a transistor (T1) having an input electrode, and output electrode which is connected to the said second power supply line (VSS) and a control electrode; and means (D4) for connecting the gate of the said first thyristor (TH1) to the said input electrode; (vii) differential amplifier means (A) having first and second inputs and an output, the output of the said differential amplifier means being connected to the control electrode of the said transistor (T1), a resistor bridge (R1R2) connecting the power supply inputs (b1-b2) of the signal generating means to the first input of the differential amplifier means, and first resistance means (R3) connecting the second power supply line (VSS) to the second input of the differential amplifier means; (viii) a first capacitor (C5); means (D6) for connecting said capacitor to the cathode of the Zener diode (Z3), means (R14) for connecting said first capacitor to the anode of the Zener diode (Z3), and means (R8) connecting the capacitor to the first power supply input (b1) of the signal generating means; (ix) means (R14R15R16D3), connecting the anode of the Zener diode (Z3) to the second input of the differential amplifier means, whereby the said transistor (T1) which is normally blocked whenever the signal generating means provide an output signal, becomes saturated upon occurrence of an overload or short through the load, and consequently, the said first thyristor (TH1) is blocked.
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