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Memory array with redundant elements 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-007/00
출원번호 US-0309694 (1981-10-08)
발명자 / 주소
  • Kressel Henry (Elizabeth NJ) Hsu Sheng T. (Lawrenceville NJ)
출원인 / 주소
  • RCA Corporation (New York NY 02)
인용정보 피인용 횟수 : 48  인용 특허 : 3

초록

A memory array formed on a single chip is provided with at least one redundant column (or row) of memory cells in addition to “standard”number of columns and rows where the spare column (or row) of cells is designed to be substituted for a standard column (or row) found to have defective cells. Prog

대표청구항

A monolithic integrated circuit comprising: a standard memory array of cells arranged in rows and columns, with a row conductor per row of cells and a column conductor per column of cells; a row decoder and a column decoder; means coupling the row decoder to the row conductors; a plurality of progra

이 특허에 인용된 특허 (3)

  1. Choate William Clay (Dallas TX), Fault-tolerant cell addressable array.
  2. Choate William Clay (Dallas TX) Bhandarkar Dileep P. (Richardson TX), Fault-tolerant cell addressable array.
  3. Cenker Ronald P. (Coplay PA) Procyk Frank J. (Center Valley PA), Memory with redundant rows and columns.

이 특허를 인용한 특허 (48)

  1. Morton Steven G. (Oxford CT), Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits.
  2. McClure David C., Circuit and method for replacing a defective memory cell with a redundant memory cell.
  3. Petro Estakhri, Data pipelining method and apparatus for memory control circuit.
  4. Hagiwara Takaaki (Kodaira JPX) Horiuchi Masatada (Koganei JPX) Kondo Ryuji (Kodaira JPX) Yatsuda Yuji (Kanagawa JPX) Minami Shinichi (Hachioji JPX), Defect-remediable semiconductor integrated circuit memory and spare substitution method in the same.
  5. Takata Akira (Toyonaka JPX), EPROM memory device having a test circuit.
  6. Deas Alexander Roger,GBX, Fault tolerant memory system.
  7. Harari Eliyahou, Flash EEPROM memory systems and methods of using them.
  8. Harari Eliyahou, Flash EEPROM system with storage of sector characteristic information within the sector.
  9. Eliyahou Harari ; Robert D. Norman ; Sanjay Mehrotra, Flash EEprom system.
  10. Harari Eliyahou (Los Gatos CA) Norman Robert D. (San Jose CA) Mehrotra Sanjay (Milpitas CA), Flash EEprom system.
  11. Harari Eliyahou ; Norman Robert D. ; Mehrotra Sanjay, Flash EEprom system.
  12. Harari, Eliyahou; Norman, Robert D.; Mehrotra, Sanjay, Flash EEprom system.
  13. Harari, Eliyahou; Norman, Robert D.; Mehrotra, Sanjay, Flash EEprom system.
  14. Harari, Eliyahou; Norman, Robert D.; Mehrotra, Sanjay, Flash EEprom system.
  15. Harari, Eliyahou; Norman, Robert D.; Mehrotra, Sanjay, Flash EEprom system.
  16. Harari, Eliyahou; Norman, Robert D.; Mehrotra, Sanjay, Flash EEprom system.
  17. Harari,Eliyahou; Norman,Robert D.; Mehrotra,Sanjay, Flash EEprom system.
  18. Harari,Eliyahou; Norman,Robert D.; Mehrotra,Sanjay, Flash EEprom system.
  19. Harari,Eliyahou; Norman,Robert D.; Mehrotra,Sanjay, Flash EEprom system.
  20. Harari, Eliyahou, Flash EEprom system with overhead data stored in user data sectors.
  21. Yaniv Zvi (Southfield MI) Cannella Vincent D. (Birmingham MI) Hansell Gregory L. (Ann Arbor MI) Johnson Robert R. (Franklin MI), High yield liquid crystal display and method of making same.
  22. Harari Eliyahou, Highly compact EPROM and flash EEPROM devices.
  23. Harari, Eliyahou, Highly compact EPROM and flash EEPROM devices.
  24. Harari, Eliyahou, Highly compact EPROM and flash EEPROM devices.
  25. Estakhri Petro ; Iman Berhanu, Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices.
  26. Estakhri, Petro; Iman, Berhanu, Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices.
  27. Estakhri, Petro; Iman, Berhanu, Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices.
  28. Petro Estakhri ; Berhanu Iman, Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices.
  29. Singh Shanker (Fishkill NY) Singh Vijendra P. (Saratoga CA), Memory correction scheme using spare arrays.
  30. Estakhri, Petro, Method and apparatus for memory control circuit.
  31. Ghneim Said N. ; Fulford ; Jr. H. Jim, Method of making non-volatile memory device having a floating gate with enhanced charge retention.
  32. Harari Eliyahou ; Norman Robert D. ; Mehrotra Sanjay, Multi-state Flash EEprom system on a card that includes defective cell substitution.
  33. Harari Eliyahou, Multi-state flash EEPROM system with defect management including an error correction scheme.
  34. Harari Eliyahou ; Norman Robert D. ; Mehrotra Sanjay, Multi-state flash EEprom system with cache memory.
  35. Harari Eliyahou ; Norman Robert D. ; Mehrotra Sanjay, Multi-state flash EEprom system with defect handling.
  36. Ghneim Said N. ; Fulford ; Jr. H. Jim, Non-volatile memory device having a floating gate with enhanced charge retention.
  37. Estakhri, Petro; Nemazie, Siamack; Assar, Mahmud; Keshtbod, Parviz, Nonvolatile memory using flexible erasing methods and method and system for using same.
  38. Petro Estakhri ; Siamack Nemazie ; Mahmud Assar ; Parviz Keshtbod, Nonvolatile memory using flexible erasing methods and method and system for using same.
  39. Futatsuya Tomoshi (Hyogo-ken JPX) Mihara Masaaki (Hyogo-ken JPX) Terada Yasushi (Hyogo-ken JPX) Nakayama Takeshi (Hyogo-ken JPX) Miyawaki Yoshikazu (Hyogo-ken JPX) Kobayashi Shinichi (Hyogo-ken JPX) , Nonvolatile semiconductor memory device with a row redundancy circuit.
  40. Valasek, Josef, Parallel accessible memory system enabling the simultaneous access to bytes of data.
  41. Smith, Teresa B.; Smith, Philip C., Programmable redundancy circuit.
  42. Shah Siddharth R. (Hopewell Junction NY) Singh Shanker (Fishkill NY) Singh Vijendra P. (Saratoga CA), Reconfigurable memory using both address permutation and spare memory elements.
  43. Lim Hyung-Kyu (Suwon KRX) Do Jae-Yeong (Dongjak CA KRX) Mehta Rustam (Sunnyvale CA), Redundancy circuit for use in a semiconductor memory device.
  44. Anderson James M. (Campbell CA) Knight ; III Thomas S. (Sunnyvale CA) Kitagawa Dennis T. (San Jose CA) Rey Ernesto (San Jose CA), Self repairing bulk memory.
  45. Ochii Kiyofumi (Yokohama JPX), Semiconductor device with spare memory cells.
  46. Horii Takashi (Kawasaki JPX) Nakano Tomio (Kawasaki JPX) Nakano Masao (Kawasaki JPX) Tsuge Norihisa (Kamakura JPX) Ogawa Junji (Yokohama JPX), Semiconductor integrated circuit.
  47. Higuchi Mitsuo (Tokyo JPX) Hagihara Ryoji (Kawasaki JPX), Semiconductor memory device.
  48. Harari Eliyahou, Techniques of programming and erasing an array of multi-state flash EEPROM cells including comparing the states of the c.
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