초록 ▼

A synchronization scheme is used in a peripheral unit controller which consists of two duplicated units whose outputs are matched. In addition, each duplicated unit contains a pair of microprocessors whose outputs are also matched. The synchronization scheme allows each microprocessor to run its own

A synchronization scheme is used in a peripheral unit controller which consists of two duplicated units whose outputs are matched. In addition, each duplicated unit contains a pair of microprocessors whose outputs are also matched. The synchronization scheme allows each microprocessor to run its own diagnostics independently, and to synchronize itself with the other microprocessor of the pair. After the synchronization occurs in both microprocessor pairs, the duplicated units are synchronized. Synchronization is achieved by using a real-time clock and the interrupt structure of each microprocessor.

대표청구항 ▼

In a data processing system including a peripheral unit controller comprising duplicated first and second subprocessors for improved reliability and a first timer circuit external to said subprocessors for controlling the synchronous starting of said subprocessors, said system comprising: a processo

In a data processing system including a peripheral unit controller comprising duplicated first and second subprocessors for improved reliability and a first timer circuit external to said subprocessors for controlling the synchronous starting of said subprocessors, said system comprising: a processor adapted to generate and transmit a plurality of peripheral orders to said first and second subprocessors; and transmission means interconnecting said processor and said subprocessors; said first timer circuit being responsive to a first timer start signal to generate a first timer completion signal a predetermined period of time after the occurence of said first timer start signal; said first subprocessor having a halt state and being responsive to a first one of said peripheral orders received from said transmission means to generate said first timer start signal and to enter its halt state; said second subprocessor having a halt state and being responsive to a second one of said peripheral orders received on said transmission means to enter its halt state and said first and said second subprocessors being responsive to said timer completion signal while in their halt state to start synchronized operation.