초록 ▼

A unique microprocessor for controlling portable and mobile cellular radiotelephones is architectured to process high speed supervisory signalling, while also minimizing power drain. The architecture of the microprocessor is organized around three buses, a data bus, a register bus and an address bus

A unique microprocessor for controlling portable and mobile cellular radiotelephones is architectured to process high speed supervisory signalling, while also minimizing power drain. The architecture of the microprocessor is organized around three buses, a data bus, a register bus and an address bus. Data signals are routed between the various blocks of the microprocessor by selectively interconnecting the three buses in response to control signals provided by ALU and control programmable logic arrays (PLA). The ALU and control PLA\s decode program instructions loaded in instruction register (IR) to provide the appropriate control signals for executing each instruction. The microprocessor also includes three general purpose registers, an arithmetic logic unit (ALU) with two temporary registers and zero and carry flags, serial data bus circuitry including a format generator and two data registers, direct I/O data direction and data registers, a stack pointer counter, a twelve-bit program counter register, a temporary program counter register and associated incrementer, and a temporary address register. Because of the unique architecture of the microprocessor, all instructions can be executed in four or less clock cycles. Moreover, the program counter register, general purpose registers and zero and carry flags are duplicated, and, during interrupts, the microprocessor switches over to the duplicate program counter register, duplicate general purpose registers and duplicate zero and carry flags. As a result, interrupts are processed quickly and efficienty merely by switching back and forth between the program counter register, general purpose registers and zero and carry flags and their duplicates. Since instruction execution time is minimized, the microprocessor can be operated at slower speeds to conserve power drain, while maintaining the through-put necessary for accommodating high-speed, cellular type supervisory signalling. Thus, a microprocessor embodying the present invention can be advantageously utilized in any application where both low power consumption and fast data manipulation are required.

대표청구항 ▼

An improved microcomputer coupled to at least one interrupt signal from a signal source and a clock signal from a signal source, said microcomputer having at least one input signal and at least one output signal and including clock and interrupt control logic coupled to the clock and interrupt signa

An improved microcomputer coupled to at least one interrupt signal from a signal source and a clock signal from a signal source, said microcomputer having at least one input signal and at least one output signal and including clock and interrupt control logic coupled to the clock and interrupt signals, respectively, said microcomputer comprising: data bus means having a plurality of data bus lines for carrying binary signals; instruction register means having a plurality of signals and being connected directly to the data bus lines for receiving signals therefrom; programmable logic means coupled to the instruction register means for providing a plurality of control signals in response to the instruction register means signals; register bus means having a plurality of register bus lines for carrying binary singals; means for intercoupling the register bus lines and data bus lines in response to predetermined ones of the programmable logic means control signals; address bus means having a plurality of address bus lines for carrying binary signals; program counter register means having a plurality of signals and further including duplicate program counter register means coupled in parallel therewith and having a plurality of signals, said program counter register means being switchably connected to the address bus lines in response to predetermined ones of the programmable logic means control signals for applying signals thereto, and said duplicate program counter register means being switchably connected to the address bus lines in place of the program counter register means in response to the interrupt signal; incrementing means; temporary program counter register means having a plurality of signals, said temporary program counter register means switchably connected to the address bus lines or register bus lines in response to predetermined ones of the programmable logic means control signals for receiving signals from the address bus lines and register bus lines, said incrementing means coupled to the temporary program counter register means for incrementing the temporary program counter register means signals in response to predetermined ones of the programmable logic means control signals and applying the incremented temporary program counter register means signals to the program counter register means and the duplicate program counter register means, said incremented temporary program counter register means signals further being switchably connected to the register bus lines in response to predetermined ones of the programmable logic means control signals; a plurality of general purpose register means each having a plurality of signals and duplicate general purpose register means coupled in parallel therewith and having a plurality of signals, each general purpose register means switchably connected to the register bus lines in response to predetermined ones of the programmable logic means control signals for applying signals to the register bus lines and directly connected to the register bus lines for receiving signals from the register bus lines in response to predetermined ones of the programmable logic means control signals, and each duplicate general purpose register means switchably connected to the register bus lines in place of its corresponding general purpose register means in response to the interrupt signal; and first and second flip-flop means each storing corresponding condition signals and having duplicate flip-flop means coupled in parallel therewith, the condition signals being coupled to arithmetic logic means, and said duplicate flip-flop means being switchably coupled in place of the corresponding first and second flip-flop means in response to the interrupt signal; arithmetic logic means having first and second register means each having a plurality of signals, the first register means being directly connected to the data bus lines for receiving signals therefrom and the second register means being directly connected to the register bus lines for receiving signals therefrom, said arithmetic logic means combining the first and second register means signals according to predetermined combinatorial functions selected by corresponding predetermined ones of the programmable logic means control signals and storing predetermined binary states of the condition signals in the first and second flip-flop means depending on the condition of said combined first and second register means signals, and said combined first and second register means signals further being switchably applied to the register bus lines in response to a predetermined one of the programmable logic means control signals.